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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
2008 (conf/iccad/2008)


  1. CAD for displays! [Citation Graph (, )][DBLP]


  2. Network flow-based power optimization under timing constraints in MSV-driven floorplanning. [Citation Graph (, )][DBLP]


  3. What can brain researchers learn from computer engineers and vice versa? [Citation Graph (, )][DBLP]


  4. Reliable system design: models, metrics and design techniques. [Citation Graph (, )][DBLP]


  5. Architecting parallel programs. [Citation Graph (, )][DBLP]


  6. Embedded software verification: challenges and solutions. [Citation Graph (, )][DBLP]


  7. Nanolithography and CAD challenges for 32nm/22nm and beyond. [Citation Graph (, )][DBLP]


  8. Challenges at 45nm and beyond. [Citation Graph (, )][DBLP]


  9. Mixed-signal simulation challenges and solutions. [Citation Graph (, )][DBLP]


  10. More Moore: foolish, feasible, or fundamentally different? [Citation Graph (, )][DBLP]


  11. Linear constraint graph for floorplan optimization with soft blocks. [Citation Graph (, )][DBLP]


  12. A novel fixed-outline floorplanner with zero deadspace for hierarchical design. [Citation Graph (, )][DBLP]


  13. Synthesis from multi-cycle atomic actions as a solution to the timing closure problem. [Citation Graph (, )][DBLP]


  14. To SAT or not to SAT: Ashenhurst decomposition in a large scale. [Citation Graph (, )][DBLP]


  15. Boolean factoring and decomposition of logic networks. [Citation Graph (, )][DBLP]


  16. On the numbers of variables to represent sparse logic functions. [Citation Graph (, )][DBLP]


  17. Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. [Citation Graph (, )][DBLP]


  18. Temperature-aware test scheduling for multiprocessor systems-on-chip. [Citation Graph (, )][DBLP]


  19. On capture power-aware test data compression for scan-based testing. [Citation Graph (, )][DBLP]


  20. MAPS: multi-algorithm parallel circuit simulation. [Citation Graph (, )][DBLP]


  21. Yield-aware hierarchical optimization of large analog integrated circuits. [Citation Graph (, )][DBLP]


  22. Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems. [Citation Graph (, )][DBLP]


  23. Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. [Citation Graph (, )][DBLP]


  24. Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. [Citation Graph (, )][DBLP]


  25. PaRS: fast and near-optimal grid-based cell sizing for library-based design. [Citation Graph (, )][DBLP]


  26. A polynomial time approximation scheme for timing constrained minimum cost layer assignment. [Citation Graph (, )][DBLP]


  27. On the decreasing significance of large standard cells in technology mapping. [Citation Graph (, )][DBLP]


  28. Verification of arithmetic datapaths using polynomial function models and congruence solving. [Citation Graph (, )][DBLP]


  29. Automated abstraction by incremental refinement in interpolant-based model checking. [Citation Graph (, )][DBLP]


  30. A succinct memory model for automated design debugging. [Citation Graph (, )][DBLP]


  31. The analysis of cyclic circuits with Boolean satisfiability. [Citation Graph (, )][DBLP]


  32. System-level power estimation using an on-chip bus performance monitoring unit. [Citation Graph (, )][DBLP]


  33. Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing. [Citation Graph (, )][DBLP]


  34. Accurate energy breakeven time estimation for run-time power gating. [Citation Graph (, )][DBLP]


  35. Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. [Citation Graph (, )][DBLP]


  36. Efficient block-based parameterized timing analysis covering all potentially critical paths. [Citation Graph (, )][DBLP]


  37. Adjustment-based modeling for statistical static timing analysis with high dimension of variability. [Citation Graph (, )][DBLP]


  38. Post-silicon timing characterization by compressed sensing. [Citation Graph (, )][DBLP]


  39. Practical, fast Monte Carlo statistical static timing analysis: why and how. [Citation Graph (, )][DBLP]


  40. On efficient Monte Carlo-based statistical static timing analysis of digital circuits. [Citation Graph (, )][DBLP]


  41. Pyramids: an efficient computational geometry-based approach for timing-driven placement. [Citation Graph (, )][DBLP]


  42. Guiding global placement with wire density. [Citation Graph (, )][DBLP]


  43. Constraint graph-based macro placement for modern mixed-size circuit designs. [Citation Graph (, )][DBLP]


  44. Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. [Citation Graph (, )][DBLP]


  45. A novel sequential circuit optimization with clock gating logic. [Citation Graph (, )][DBLP]


  46. Scalable and scalably-verifiable sequential synthesis. [Citation Graph (, )][DBLP]


  47. System-level thermal aware design of applications with uncertain execution time. [Citation Graph (, )][DBLP]


  48. Proactive temperature balancing for low cost thermal management in MPSoCs. [Citation Graph (, )][DBLP]


  49. A framework for predictive dynamic temperature management of microprocessor systems. [Citation Graph (, )][DBLP]


  50. A voltage-frequency island aware energy optimization framework for networks-on-chip. [Citation Graph (, )][DBLP]


  51. Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. [Citation Graph (, )][DBLP]


  52. Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits. [Citation Graph (, )][DBLP]


  53. A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. [Citation Graph (, )][DBLP]


  54. Linear analysis of random process variability. [Citation Graph (, )][DBLP]


  55. Design and optimization of a digital microfluidic biochip for protein crystallization. [Citation Graph (, )][DBLP]


  56. Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. [Citation Graph (, )][DBLP]


  57. Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. [Citation Graph (, )][DBLP]


  58. Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example. [Citation Graph (, )][DBLP]


  59. Breaking the simulation barrier: SRAM evaluation through norm minimization. [Citation Graph (, )][DBLP]


  60. Power supply noise aware workload assignment for multi-core systems. [Citation Graph (, )][DBLP]


  61. NTHU-Route 2.0: a fast and stable global router. [Citation Graph (, )][DBLP]


  62. FastRoute3.0: a fast and high quality global router based on virtual capacity. [Citation Graph (, )][DBLP]


  63. Multi-layer global routing considering via and wire capacities. [Citation Graph (, )][DBLP]


  64. Race analysis for SystemC using model checking. [Citation Graph (, )][DBLP]


  65. MC-Sim: an efficient simulation tool for MPSoC designs. [Citation Graph (, )][DBLP]


  66. Verifying external interrupts of embedded microprocessor in SoC with on-chip bus. [Citation Graph (, )][DBLP]


  67. SRAM dynamic stability: theory, variability and analysis. [Citation Graph (, )][DBLP]


  68. Impulse sensitivity function analysis of periodic circuits. [Citation Graph (, )][DBLP]


  69. Automated extraction of expert knowledge in analog topology selection and sizing. [Citation Graph (, )][DBLP]


  70. Importance sampled circuit learning ensembles for robust analog IC design. [Citation Graph (, )][DBLP]


  71. Physical models for electron transport in graphene nanoribbons and their junctions. [Citation Graph (, )][DBLP]


  72. Characterization and modeling of graphene field-effect devices. [Citation Graph (, )][DBLP]


  73. Graphene nanoribbon FETs: technology exploration and CAD. [Citation Graph (, )][DBLP]


  74. Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. [Citation Graph (, )][DBLP]


  75. Decoupling capacitance allocation for timing with statistical noise model and timing analysis. [Citation Graph (, )][DBLP]


  76. Transition-aware decoupling-capacitor allocation in power noise reduction. [Citation Graph (, )][DBLP]


  77. Placement based multiplier rewiring for cell-based designs. [Citation Graph (, )][DBLP]


  78. Correct-by-construction microarchitectural pipelining. [Citation Graph (, )][DBLP]


  79. Performance optimization of elastic systems using buffer resizing and buffer insertion. [Citation Graph (, )][DBLP]


  80. Performance estimation and slack matching for pipelined asynchronous architectures with choice. [Citation Graph (, )][DBLP]


  81. Diastolic arrays: throughput-driven reconfigurable computing. [Citation Graph (, )][DBLP]


  82. Layout decomposition for double patterning lithography. [Citation Graph (, )][DBLP]


  83. Electrically driven optical proximity correction based on linear programming. [Citation Graph (, )][DBLP]


  84. A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique. [Citation Graph (, )][DBLP]


  85. Overlay aware interconnect and timing variation modeling for double patterning technology. [Citation Graph (, )][DBLP]


  86. Exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinates. [Citation Graph (, )][DBLP]


  87. BSG-Route: a length-matching router for general topology. [Citation Graph (, )][DBLP]


  88. Double patterning technology friendly detailed routing. [Citation Graph (, )][DBLP]


  89. Routing for chip-package-board co-design considering differential pairs. [Citation Graph (, )][DBLP]


  90. Area-I/O flip-chip routing for chip-package co-design. [Citation Graph (, )][DBLP]


  91. Obstacle-avoiding rectilinear Steiner tree construction. [Citation Graph (, )][DBLP]


  92. Evaluation of voltage interpolation to address process variations. [Citation Graph (, )][DBLP]


  93. Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. [Citation Graph (, )][DBLP]


  94. ROAdNoC: runtime observability for an adaptive network on chip architecture. [Citation Graph (, )][DBLP]


  95. FBT: filled buffer technique to reduce code size for VLIW processors. [Citation Graph (, )][DBLP]


  96. Advancing supercomputer performance through interconnection topology synthesis. [Citation Graph (, )][DBLP]


  97. Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. [Citation Graph (, )][DBLP]


  98. SPM management using Markov chain based data access prediction. [Citation Graph (, )][DBLP]


  99. Process variation aware system-level task allocation using stochastic ordering of delay distributions. [Citation Graph (, )][DBLP]


  100. Game-theoretic timing analysis. [Citation Graph (, )][DBLP]


  101. Integrated code and data placement in two-dimensional mesh based chip multiprocessors. [Citation Graph (, )][DBLP]


  102. Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. [Citation Graph (, )][DBLP]


  103. On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications. [Citation Graph (, )][DBLP]


  104. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. [Citation Graph (, )][DBLP]


  105. ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits. [Citation Graph (, )][DBLP]


  106. Parameterized transient thermal behavioral modeling for chip multiprocessors. [Citation Graph (, )][DBLP]


  107. Temperature aware task sequencing and voltage scaling. [Citation Graph (, )][DBLP]


  108. Statistical path selection for at-speed test. [Citation Graph (, )][DBLP]


  109. Power supply signal calibration techniques for improving detection resolution to hardware Trojans. [Citation Graph (, )][DBLP]


  110. Path-RO: a novel on-chip critical path delay measurement under process variations. [Citation Graph (, )][DBLP]


  111. Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms. [Citation Graph (, )][DBLP]


  112. Efficient and accurate eye diagram prediction for high speed signaling. [Citation Graph (, )][DBLP]


  113. A capacitance solver for incremental variation-aware extraction. [Citation Graph (, )][DBLP]


  114. Lightweight secure PUFs. [Citation Graph (, )][DBLP]


  115. Hardware protection and authentication through netlist level obfuscation. [Citation Graph (, )][DBLP]


  116. MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. [Citation Graph (, )][DBLP]


  117. Process variability-aware transient fault modeling and analysis. [Citation Graph (, )][DBLP]


  118. STEEL: a technique for stress-enhanced standard cell library design. [Citation Graph (, )][DBLP]


  119. A statistical approach for full-chip gate-oxide reliability analysis. [Citation Graph (, )][DBLP]


  120. Robust FPGA resynthesis based on fault-tolerant Boolean matching. [Citation Graph (, )][DBLP]


  121. Fault tolerant placement and defect reconfiguration for nano-FPGAs. [Citation Graph (, )][DBLP]


  122. Thermal-aware reliability analysis for platform FPGAs. [Citation Graph (, )][DBLP]


  123. Guaranteed stable projection-based model reduction for indefinite and unstable linear systems. [Citation Graph (, )][DBLP]


  124. Sparse implicit projection (SIP) for reduction of general many-terminal networks. [Citation Graph (, )][DBLP]


  125. Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. [Citation Graph (, )][DBLP]


  126. Integrated circuit design with NEM relays. [Citation Graph (, )][DBLP]


  127. Module locking in biochemical synthesis. [Citation Graph (, )][DBLP]


  128. Robust reconfigurable filter design using analytic variability quantification techniques. [Citation Graph (, )][DBLP]


  129. Using test data to improve IC quality and yield. [Citation Graph (, )][DBLP]


  130. Silicon feedback to improve frequency of high-performance microprocessors: an overview. [Citation Graph (, )][DBLP]


  131. Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking method. [Citation Graph (, )][DBLP]


  132. Constrained aggressor set selection for maximum coupling noise. [Citation Graph (, )][DBLP]


  133. Context-sensitive static transistor-level IR analysis. [Citation Graph (, )][DBLP]


  134. Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis. [Citation Graph (, )][DBLP]


  135. Smoothed form of nonlinear phase macromodel for oscillators. [Citation Graph (, )][DBLP]


  136. Comprehensive procedure for fast and accurate coupled oscillator network simulation. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002