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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
2009 (conf/iccad/2009)


  1. First steps towards SAT-based formal analog verification. [Citation Graph (, )][DBLP]


  2. Interpolant generation without constructing resolution graph. [Citation Graph (, )][DBLP]


  3. A scalable decision procedure for fixed-width bit-vectors. [Citation Graph (, )][DBLP]


  4. Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. [Citation Graph (, )][DBLP]


  5. Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection. [Citation Graph (, )][DBLP]


  6. How to consider shorts and guarantee yield rate improvement for redundant wire insertion. [Citation Graph (, )][DBLP]


  7. Power-switch routing for coarse-grain MTCMOS technologies. [Citation Graph (, )][DBLP]


  8. Scheduling with soft constraints. [Citation Graph (, )][DBLP]


  9. REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. [Citation Graph (, )][DBLP]


  10. Enhanced reliability-aware power management through shared recovery technique. [Citation Graph (, )][DBLP]


  11. Resilient circuits - Enabling energy-efficient performance and reliability. [Citation Graph (, )][DBLP]


  12. Resilience in computer systems and networks. [Citation Graph (, )][DBLP]


  13. Scan power reduction in linear test data compression scheme. [Citation Graph (, )][DBLP]


  14. Compacting test vector sets via strategic use of implications. [Citation Graph (, )][DBLP]


  15. Pre-ATPG path selection for near optimal post-ATPG process space coverage. [Citation Graph (, )][DBLP]


  16. A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. [Citation Graph (, )][DBLP]


  17. IPR: In-Place Reconfiguration for FPGA fault tolerance. [Citation Graph (, )][DBLP]


  18. A circuit-software co-design approach for improving EDP in reconfigurable frameworks. [Citation Graph (, )][DBLP]


  19. Security against hardware Trojan through a novel application of design obfuscation. [Citation Graph (, )][DBLP]


  20. MOLES: Malicious off-chip leakage enabled by side-channels. [Citation Graph (, )][DBLP]


  21. Consistency-based characterization for IC Trojan detection. [Citation Graph (, )][DBLP]


  22. SAT-based protein design. [Citation Graph (, )][DBLP]


  23. Synthesizing sequential register-based computation with biochemistry. [Citation Graph (, )][DBLP]


  24. An algorithm for identifying dominant-edge metabolic pathways. [Citation Graph (, )][DBLP]


  25. A contamination aware droplet routing algorithm for digital microfluidic biochips. [Citation Graph (, )][DBLP]


  26. On soft error rate analysis of scaled CMOS designs - A statistical perspective. [Citation Graph (, )][DBLP]


  27. Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. [Citation Graph (, )][DBLP]


  28. DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. [Citation Graph (, )][DBLP]


  29. A variation-aware preferential design approach for memory based reconfigurable computing. [Citation Graph (, )][DBLP]


  30. Pre-bond testable low-power clock tree design for 3D stacked ICs. [Citation Graph (, )][DBLP]


  31. Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. [Citation Graph (, )][DBLP]


  32. BIST design optimization for large-scale embedded memory cores. [Citation Graph (, )][DBLP]


  33. Operating system scheduling for efficient online self-test in robust systems. [Citation Graph (, )][DBLP]


  34. Quantifying robustness metrics in parameterized static timing analysis. [Citation Graph (, )][DBLP]


  35. PSTA-based branch and bound approach to the silicon speedpath isolation problem. [Citation Graph (, )][DBLP]


  36. Timing Arc based logic analysis for false noise reduction. [Citation Graph (, )][DBLP]


  37. Exact route matching algorithms for analog and mixed signal integrated circuits. [Citation Graph (, )][DBLP]


  38. An efficient pre-assignment routing algorithm for flip-chip designs. [Citation Graph (, )][DBLP]


  39. Optimal layer assignment for escape routing of buses. [Citation Graph (, )][DBLP]


  40. Pad assignment for die-stacking System-in-Package design. [Citation Graph (, )][DBLP]


  41. Thermal modeling for 3D-ICs with integrated microchannel cooling. [Citation Graph (, )][DBLP]


  42. Energy reduction for STT-RAM using early write termination. [Citation Graph (, )][DBLP]


  43. PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. [Citation Graph (, )][DBLP]


  44. The epsilon-approximation to discrete VT assignment for leakage power minimization. [Citation Graph (, )][DBLP]


  45. A rigorous framework for convergent net weighting schemes in timing-driven placement. [Citation Graph (, )][DBLP]


  46. An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis. [Citation Graph (, )][DBLP]


  47. TAPE: Thermal-aware agent-based power econom multi/many-core architectures. [Citation Graph (, )][DBLP]


  48. Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. [Citation Graph (, )][DBLP]


  49. A hybrid local-global approach for multi-core thermal management. [Citation Graph (, )][DBLP]


  50. A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. [Citation Graph (, )][DBLP]


  51. Binning optimization based on SSTA for transparently-latched circuits. [Citation Graph (, )][DBLP]


  52. Timing model extraction for sequential circuits considering process variations. [Citation Graph (, )][DBLP]


  53. CROP: Fast and effective congestion refinement of placement. [Citation Graph (, )][DBLP]


  54. GRPlacer: Improving routability and wire-length of global routing with circuit replacement. [Citation Graph (, )][DBLP]


  55. CRISP: Congestion reduction by iterated spreading during placement. [Citation Graph (, )][DBLP]


  56. A study of routability estimation and clustering in placement. [Citation Graph (, )][DBLP]


  57. The synthesis of combinational logic to generate probabilities. [Citation Graph (, )][DBLP]


  58. Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. [Citation Graph (, )][DBLP]


  59. Synthesizing complementary circuits automatically. [Citation Graph (, )][DBLP]


  60. QLMOR: A new projection-based approach for nonlinear model order reduction. [Citation Graph (, )][DBLP]


  61. Computing quadratic approximations for the isochrons of oscillators: A general theory and advanced numerical methods. [Citation Graph (, )][DBLP]


  62. Final-value ODEs: Stable numerical integration and its application to parallel circuit analysis. [Citation Graph (, )][DBLP]


  63. A parallel preconditioning strategy for efficient transistor-level circuit simulation. [Citation Graph (, )][DBLP]


  64. Characterizing within-die variation from multiple supply port IDDQ measurements. [Citation Graph (, )][DBLP]


  65. Voltage binning under process variation. [Citation Graph (, )][DBLP]


  66. Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. [Citation Graph (, )][DBLP]


  67. Post-fabrication measurement-driven oxide breakdown reliability prediction and management. [Citation Graph (, )][DBLP]


  68. Minimizing expected energy consumption through optimal integration of DVS and DPM. [Citation Graph (, )][DBLP]


  69. An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs. [Citation Graph (, )][DBLP]


  70. Adaptive power management using reinforcement learning. [Citation Graph (, )][DBLP]


  71. Temporal and spatial idleness exploitation for optimal-grained leakage control. [Citation Graph (, )][DBLP]


  72. A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. [Citation Graph (, )][DBLP]


  73. Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. [Citation Graph (, )][DBLP]


  74. Nonvolatile memristor memory: Device characteristics and design implications. [Citation Graph (, )][DBLP]


  75. Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification. [Citation Graph (, )][DBLP]


  76. An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. [Citation Graph (, )][DBLP]


  77. Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. [Citation Graph (, )][DBLP]


  78. Modeling of layout-dependent stress effect in CMOS design. [Citation Graph (, )][DBLP]


  79. Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization. [Citation Graph (, )][DBLP]


  80. Leveraging efficient parallel pattern search for clock mesh optimization. [Citation Graph (, )][DBLP]


  81. Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. [Citation Graph (, )][DBLP]


  82. Taming irregular EDA applications on GPUs. [Citation Graph (, )][DBLP]


  83. Multi-level clustering for clock skew optimization. [Citation Graph (, )][DBLP]


  84. From 2D to 3D NoCs: A case study on worst-case communication performance. [Citation Graph (, )][DBLP]


  85. An accurate and efficient performance analysis approach based on queuing model for network on chip. [Citation Graph (, )][DBLP]


  86. A performance analytical model for Network-on-Chip with constant service time routers. [Citation Graph (, )][DBLP]


  87. A method for calculating hard QoS guarantees for Networks-on-Chip. [Citation Graph (, )][DBLP]


  88. Task management in MPSoCs: An ASIP approach. [Citation Graph (, )][DBLP]


  89. Simultaneous layout migration and decomposition for double patterning technology. [Citation Graph (, )][DBLP]


  90. GREMA: Graph reduction based efficient mask assignment for double patterning technology. [Citation Graph (, )][DBLP]


  91. Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. [Citation Graph (, )][DBLP]


  92. A framework for early and systematic evaluation of design rules. [Citation Graph (, )][DBLP]


  93. Adaptive sampling for efficient failure probability analysis of SRAM cells. [Citation Graph (, )][DBLP]


  94. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]


  95. Mitigation of intra-array SRAM variability using adaptive voltage architecture. [Citation Graph (, )][DBLP]


  96. Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs. [Citation Graph (, )][DBLP]


  97. Energy-optimal dynamic thermal management for green computing. [Citation Graph (, )][DBLP]


  98. Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. [Citation Graph (, )][DBLP]


  99. Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. [Citation Graph (, )][DBLP]


  100. A study of Through-Silicon-Via impact on the 3D stacked IC layout. [Citation Graph (, )][DBLP]


  101. Parallel multi-level analytical global placement on graphics processing units. [Citation Graph (, )][DBLP]


  102. Memory organization and data layout for instruction set extensions with architecturally visible storage. [Citation Graph (, )][DBLP]


  103. Automatic memory partitioning and scheduling for throughput and power optimization. [Citation Graph (, )][DBLP]


  104. Battery allocation for wireless sensor network lifetime maximization under cost constraints. [Citation Graph (, )][DBLP]


  105. Genetic design automation. [Citation Graph (, )][DBLP]


  106. An electrical-level superposed-edge approach to statistical serial link simulation. [Citation Graph (, )][DBLP]


  107. Joint design-time and post-silicon optimization for digitally tuned analog circuits. [Citation Graph (, )][DBLP]


  108. Fast trade-off evaluation for digital signal processing systems during wordlength optimization. [Citation Graph (, )][DBLP]


  109. Improved heuristics for finite word-length polynomial datapath optimization. [Citation Graph (, )][DBLP]


  110. Decoupling capacitance efficient placement for reducing transient power supply noise. [Citation Graph (, )][DBLP]


  111. A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction. [Citation Graph (, )][DBLP]


  112. Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passives. [Citation Graph (, )][DBLP]


  113. GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems. [Citation Graph (, )][DBLP]


  114. Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil. [Citation Graph (, )][DBLP]


  115. Interpolating functions from large Boolean relations. [Citation Graph (, )][DBLP]


  116. Fast detection of node mergers using logic implications. [Citation Graph (, )][DBLP]


  117. DeltaSyn: An efficient logic difference optimizer for ECO synthesis. [Citation Graph (, )][DBLP]


  118. Iterative layering: Optimizing arithmetic circuits by structuring the information flow. [Citation Graph (, )][DBLP]


  119. Global routing revisited. [Citation Graph (, )][DBLP]


  120. POWER7 - Verification challenge of a multi-core processor. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002