Conferences in DBLP
Design and Implementation of Software Objects in Hardware. [Citation Graph (, )][DBLP ] RasP: An Area-efficient, On-chip Network. [Citation Graph (, )][DBLP ] Power-Constrained SOC Test Schedules through Utilization of Functional Buses. [Citation Graph (, )][DBLP ] Power/ground supply network optimization for power-gating. [Citation Graph (, )][DBLP ] Reduce Register Files Leakage Through Discharging Cells. [Citation Graph (, )][DBLP ] Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. [Citation Graph (, )][DBLP ] Seqver : A Sequential Equivalence Verifier for Hardware Designs . [Citation Graph (, )][DBLP ] Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. [Citation Graph (, )][DBLP ] Iterative-Constructive Standard Cell Placer for High Speed and Low Power. [Citation Graph (, )][DBLP ] Implementation and Evaluation of On-Chip Network Architectures. [Citation Graph (, )][DBLP ] An Enhancement for a Scheduling Logic Pipelined over two Cycles . [Citation Graph (, )][DBLP ] Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . [Citation Graph (, )][DBLP ] Interconnect Considerations For High Performance Network on Chip Designs. [Citation Graph (, )][DBLP ] Computer Architecture in the Many-Core Era. [Citation Graph (, )][DBLP ] FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. [Citation Graph (, )][DBLP ] Partial Functional Manipulation Based Wirelength Minimization. [Citation Graph (, )][DBLP ] Requirements and Concepts for Transaction Level Assertions. [Citation Graph (, )][DBLP ] A Pattern Generation Technique for Maximizing Power Supply Currents. [Citation Graph (, )][DBLP ] Long-term Performance Bottleneck Analysis and Prediction. [Citation Graph (, )][DBLP ] On the Improvement of Statistical Static Timing Analysis. [Citation Graph (, )][DBLP ] RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. [Citation Graph (, )][DBLP ] Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors. [Citation Graph (, )][DBLP ] Microarchitecture and Performance Analysis of Godson-2 SMT Processor. [Citation Graph (, )][DBLP ] Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. [Citation Graph (, )][DBLP ] Reconfigurable CAM Architecture for Network Search Engines. [Citation Graph (, )][DBLP ] Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. [Citation Graph (, )][DBLP ] A New Class of Sequential Circuits with Acyclic Test Generation Complexity. [Citation Graph (, )][DBLP ] Reduction of Crosstalk Pessimism using Tendency Graph Approach. [Citation Graph (, )][DBLP ] An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. [Citation Graph (, )][DBLP ] Power Droop Testing. [Citation Graph (, )][DBLP ] Customizable Fault Tolerant Caches for Embedded Processors. [Citation Graph (, )][DBLP ] Patching Processor Design Errors. [Citation Graph (, )][DBLP ] Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. [Citation Graph (, )][DBLP ] Delay and Area Efficient First-level Cache Soft Error Detection and Correction. [Citation Graph (, )][DBLP ] Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems. [Citation Graph (, )][DBLP ] Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. [Citation Graph (, )][DBLP ] Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. [Citation Graph (, )][DBLP ] CMOS Comparators for High-Speed and Low-Power Applications. [Citation Graph (, )][DBLP ] Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation. [Citation Graph (, )][DBLP ] FPGA Implementation of High Speed FIR Filters Using Add and Shift Method. [Citation Graph (, )][DBLP ] Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. [Citation Graph (, )][DBLP ] Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. [Citation Graph (, )][DBLP ] Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. [Citation Graph (, )][DBLP ] Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. [Citation Graph (, )][DBLP ] A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems. [Citation Graph (, )][DBLP ] Speculative Code Value Specialization Using the Trace Cache Fill Unit. [Citation Graph (, )][DBLP ] Welcome Message. [Citation Graph (, )][DBLP ] Organizing Committee. [Citation Graph (, )][DBLP ] A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. [Citation Graph (, )][DBLP ] An Efficient, Scalable Hardware Engine for Boolean SATisfiability. [Citation Graph (, )][DBLP ] A theory of Error-Rate Testing. [Citation Graph (, )][DBLP ] Polaris: A System-Level Roadmap for On-Chip Interconnection Networks. [Citation Graph (, )][DBLP ] High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding. [Citation Graph (, )][DBLP ] A Low Power Highly Associative Cache for Embedded Systems. [Citation Graph (, )][DBLP ] Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. [Citation Graph (, )][DBLP ] Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. [Citation Graph (, )][DBLP ] Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing. [Citation Graph (, )][DBLP ] System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. [Citation Graph (, )][DBLP ] Improving Power and Data Efficiency with Threaded Memory Modules. [Citation Graph (, )][DBLP ] Simulation-based functional test justification using a decision-digram-based Boolean data miner. [Citation Graph (, )][DBLP ] Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP ] Addressing Multicore Communication Challenges Using NoC Technology. [Citation Graph (, )][DBLP ] Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. [Citation Graph (, )][DBLP ] Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. [Citation Graph (, )][DBLP ] A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips. [Citation Graph (, )][DBLP ] Assertion-Based Microarchitecture Design for Improved Reliability. [Citation Graph (, )][DBLP ] FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. [Citation Graph (, )][DBLP ] Scaling Manufacturability Software to Thousands of Processors. [Citation Graph (, )][DBLP ] Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP ] Trends and Future Directions in Nano Structure Based Computing and Fabrication. [Citation Graph (, )][DBLP ] Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . [Citation Graph (, )][DBLP ] Clustering-Based Microcode Compression. [Citation Graph (, )][DBLP ] Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. [Citation Graph (, )][DBLP ] Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD. [Citation Graph (, )][DBLP ] Guiding Architectural SRAM Models. [Citation Graph (, )][DBLP ] Efficient Testing of RF MIMO Transceivers Used in WLAN Applications. [Citation Graph (, )][DBLP ] An accurate Energy estimation framework for VLIW Processor Cores. [Citation Graph (, )][DBLP ] High-Level vs. RTL Combinational Equivalence: An Introduction. [Citation Graph (, )][DBLP ] Additional Reviewers. [Citation Graph (, )][DBLP ] Architectural Support for Run-Time Validation of Control Flow Transfer. [Citation Graph (, )][DBLP ] Synthesis of Regular Logic Bricks for Robust IC Design. [Citation Graph (, )][DBLP ] Scale in Chip Interconnect requires Network Technology . [Citation Graph (, )][DBLP ] A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models. [Citation Graph (, )][DBLP ] Program Committee. [Citation Graph (, )][DBLP ] Design and Implementation of the TRIPS Primary Memory System. [Citation Graph (, )][DBLP ] Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. [Citation Graph (, )][DBLP ] 