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Conferences in DBLP

International Conference on Computer Design (ICCD) (iccd)
2006 (conf/iccd/2006)

  1. Design and Implementation of Software Objects in Hardware. [Citation Graph (, )][DBLP]

  2. RasP: An Area-efficient, On-chip Network. [Citation Graph (, )][DBLP]

  3. Power-Constrained SOC Test Schedules through Utilization of Functional Buses. [Citation Graph (, )][DBLP]

  4. Power/ground supply network optimization for power-gating. [Citation Graph (, )][DBLP]

  5. Reduce Register Files Leakage Through Discharging Cells. [Citation Graph (, )][DBLP]

  6. Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. [Citation Graph (, )][DBLP]

  7. Seqver : A Sequential Equivalence Verifier for Hardware Designs . [Citation Graph (, )][DBLP]

  8. Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. [Citation Graph (, )][DBLP]

  9. Iterative-Constructive Standard Cell Placer for High Speed and Low Power. [Citation Graph (, )][DBLP]

  10. Implementation and Evaluation of On-Chip Network Architectures. [Citation Graph (, )][DBLP]

  11. An Enhancement for a Scheduling Logic Pipelined over two Cycles . [Citation Graph (, )][DBLP]

  12. Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . [Citation Graph (, )][DBLP]

  13. Interconnect Considerations For High Performance Network on Chip Designs. [Citation Graph (, )][DBLP]

  14. Computer Architecture in the Many-Core Era. [Citation Graph (, )][DBLP]

  15. FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. [Citation Graph (, )][DBLP]

  16. Partial Functional Manipulation Based Wirelength Minimization. [Citation Graph (, )][DBLP]

  17. Requirements and Concepts for Transaction Level Assertions. [Citation Graph (, )][DBLP]

  18. A Pattern Generation Technique for Maximizing Power Supply Currents. [Citation Graph (, )][DBLP]

  19. Long-term Performance Bottleneck Analysis and Prediction. [Citation Graph (, )][DBLP]

  20. On the Improvement of Statistical Static Timing Analysis. [Citation Graph (, )][DBLP]

  21. RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. [Citation Graph (, )][DBLP]

  22. Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors. [Citation Graph (, )][DBLP]

  23. Microarchitecture and Performance Analysis of Godson-2 SMT Processor. [Citation Graph (, )][DBLP]

  24. Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. [Citation Graph (, )][DBLP]

  25. Reconfigurable CAM Architecture for Network Search Engines. [Citation Graph (, )][DBLP]

  26. Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. [Citation Graph (, )][DBLP]

  27. A New Class of Sequential Circuits with Acyclic Test Generation Complexity. [Citation Graph (, )][DBLP]

  28. Reduction of Crosstalk Pessimism using Tendency Graph Approach. [Citation Graph (, )][DBLP]

  29. An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. [Citation Graph (, )][DBLP]

  30. Power Droop Testing. [Citation Graph (, )][DBLP]

  31. Customizable Fault Tolerant Caches for Embedded Processors. [Citation Graph (, )][DBLP]

  32. Patching Processor Design Errors. [Citation Graph (, )][DBLP]

  33. Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. [Citation Graph (, )][DBLP]

  34. Delay and Area Efficient First-level Cache Soft Error Detection and Correction. [Citation Graph (, )][DBLP]

  35. Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems. [Citation Graph (, )][DBLP]

  36. Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. [Citation Graph (, )][DBLP]

  37. Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. [Citation Graph (, )][DBLP]

  38. CMOS Comparators for High-Speed and Low-Power Applications. [Citation Graph (, )][DBLP]

  39. Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation. [Citation Graph (, )][DBLP]

  40. FPGA Implementation of High Speed FIR Filters Using Add and Shift Method. [Citation Graph (, )][DBLP]

  41. Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. [Citation Graph (, )][DBLP]

  42. Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. [Citation Graph (, )][DBLP]

  43. Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. [Citation Graph (, )][DBLP]

  44. Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. [Citation Graph (, )][DBLP]

  45. A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems. [Citation Graph (, )][DBLP]

  46. Speculative Code Value Specialization Using the Trace Cache Fill Unit. [Citation Graph (, )][DBLP]

  47. Welcome Message. [Citation Graph (, )][DBLP]

  48. Organizing Committee. [Citation Graph (, )][DBLP]

  49. A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. [Citation Graph (, )][DBLP]

  50. An Efficient, Scalable Hardware Engine for Boolean SATisfiability. [Citation Graph (, )][DBLP]

  51. A theory of Error-Rate Testing. [Citation Graph (, )][DBLP]

  52. Polaris: A System-Level Roadmap for On-Chip Interconnection Networks. [Citation Graph (, )][DBLP]

  53. High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding. [Citation Graph (, )][DBLP]

  54. A Low Power Highly Associative Cache for Embedded Systems. [Citation Graph (, )][DBLP]

  55. Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. [Citation Graph (, )][DBLP]

  56. Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. [Citation Graph (, )][DBLP]

  57. Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing. [Citation Graph (, )][DBLP]

  58. System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. [Citation Graph (, )][DBLP]

  59. Improving Power and Data Efficiency with Threaded Memory Modules. [Citation Graph (, )][DBLP]

  60. Simulation-based functional test justification using a decision-digram-based Boolean data miner. [Citation Graph (, )][DBLP]

  61. Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP]

  62. Addressing Multicore Communication Challenges Using NoC Technology. [Citation Graph (, )][DBLP]

  63. Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. [Citation Graph (, )][DBLP]

  64. Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. [Citation Graph (, )][DBLP]

  65. A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips. [Citation Graph (, )][DBLP]

  66. Assertion-Based Microarchitecture Design for Improved Reliability. [Citation Graph (, )][DBLP]

  67. FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. [Citation Graph (, )][DBLP]

  68. Scaling Manufacturability Software to Thousands of Processors. [Citation Graph (, )][DBLP]

  69. Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP]

  70. Trends and Future Directions in Nano Structure Based Computing and Fabrication. [Citation Graph (, )][DBLP]

  71. Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . [Citation Graph (, )][DBLP]

  72. Clustering-Based Microcode Compression. [Citation Graph (, )][DBLP]

  73. Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. [Citation Graph (, )][DBLP]

  74. Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD. [Citation Graph (, )][DBLP]

  75. Guiding Architectural SRAM Models. [Citation Graph (, )][DBLP]

  76. Efficient Testing of RF MIMO Transceivers Used in WLAN Applications. [Citation Graph (, )][DBLP]

  77. An accurate Energy estimation framework for VLIW Processor Cores. [Citation Graph (, )][DBLP]

  78. High-Level vs. RTL Combinational Equivalence: An Introduction. [Citation Graph (, )][DBLP]

  79. Additional Reviewers. [Citation Graph (, )][DBLP]

  80. Architectural Support for Run-Time Validation of Control Flow Transfer. [Citation Graph (, )][DBLP]

  81. Synthesis of Regular Logic Bricks for Robust IC Design. [Citation Graph (, )][DBLP]

  82. Scale in Chip Interconnect requires Network Technology . [Citation Graph (, )][DBLP]

  83. A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models. [Citation Graph (, )][DBLP]

  84. Program Committee. [Citation Graph (, )][DBLP]

  85. Design and Implementation of the TRIPS Primary Memory System. [Citation Graph (, )][DBLP]

  86. Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. [Citation Graph (, )][DBLP]

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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002