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Conferences in DBLP

International Conference on Computer Design (ICCD) (iccd)
2007 (conf/iccd/2007)


  1. Twiddle factor transformation for pipelined FFT processing. [Citation Graph (, )][DBLP]


  2. Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. [Citation Graph (, )][DBLP]


  3. Speed-area optimized FPGA implementation for Full Search Block Matching. [Citation Graph (, )][DBLP]


  4. Bounded model checking of embedded software in wireless cognitive radio systems. [Citation Graph (, )][DBLP]


  5. Application of symbolic computer algebra to arithmetic circuit verification. [Citation Graph (, )][DBLP]


  6. Continual hashing for efficient fine-grain state inconsistency detection. [Citation Graph (, )][DBLP]


  7. Automatic SystemC TLM generation for custom communication platforms. [Citation Graph (, )][DBLP]


  8. Improving cache efficiency via resizing + remapping. [Citation Graph (, )][DBLP]


  9. Exploring DRAM cache architectures for CMP server platforms. [Citation Graph (, )][DBLP]


  10. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. [Citation Graph (, )][DBLP]


  11. Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. [Citation Graph (, )][DBLP]


  12. Voltage drop reduction for on-chip power delivery considering leakage current variations. [Citation Graph (, )][DBLP]


  13. On modeling impact of sub-wavelength lithography on transistors. [Citation Graph (, )][DBLP]


  14. Why we need statistical static timing analysis. [Citation Graph (, )][DBLP]


  15. Statistical timing analysis using Kernel smoothing. [Citation Graph (, )][DBLP]


  16. Tutorial: Software-defined radio technology. [Citation Graph (, )][DBLP]


  17. A position-insensitive finished store buffer. [Citation Graph (, )][DBLP]


  18. A low overhead hardware technique for software integrity and confidentiality. [Citation Graph (, )][DBLP]


  19. Cluster-level simultaneous multithreading for VLIW processors. [Citation Graph (, )][DBLP]


  20. Evaluating voltage islands in CMPs under process variations. [Citation Graph (, )][DBLP]


  21. Non-arithmetic carry chains for reconfigurable fabrics. [Citation Graph (, )][DBLP]


  22. FPGA global routing architecture optimization using a multicommodity flow approach. [Citation Graph (, )][DBLP]


  23. FPGA routing architecture analysis under variations. [Citation Graph (, )][DBLP]


  24. Energy-aware co-processor selection for embedded processors on FPGAs. [Citation Graph (, )][DBLP]


  25. Benchmarks and performance analysis of decimal floating-point applications. [Citation Graph (, )][DBLP]


  26. Multi-core data streaming architecture for ray tracing. [Citation Graph (, )][DBLP]


  27. Hardware libraries: An architecture for economic acceleration in soft multi-core environments. [Citation Graph (, )][DBLP]


  28. Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors. [Citation Graph (, )][DBLP]


  29. Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. [Citation Graph (, )][DBLP]


  30. Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. [Citation Graph (, )][DBLP]


  31. Scan chain design for three-dimensional integrated circuits (3D ICs). [Citation Graph (, )][DBLP]


  32. The challenge in testing MIMO in a Wi-Fi or WiMAX context. [Citation Graph (, )][DBLP]


  33. Challenges and prospects of SDR for mobile phones. [Citation Graph (, )][DBLP]


  34. Exploring the interplay of yield, area, and performance in processor caches. [Citation Graph (, )][DBLP]


  35. Improving the reliability of on-chip L2 cache using redundancy. [Citation Graph (, )][DBLP]


  36. Reducing leakage power in peripheral circuits of L2 caches. [Citation Graph (, )][DBLP]


  37. Two-level ata prefetching. [Citation Graph (, )][DBLP]


  38. Cache replacement based on reuse-distance prediction. [Citation Graph (, )][DBLP]


  39. Constraint satisfaction in incremental placement with application to performance optimization under power constraints. [Citation Graph (, )][DBLP]


  40. Fine grain 3D integration for microarchitecture design through cube packing exploration. [Citation Graph (, )][DBLP]


  41. Whitespace redistribution for thermal via insertion in 3D stacked ICs. [Citation Graph (, )][DBLP]


  42. Placement and routing of RF embedded passive designs in LCP substrate. [Citation Graph (, )][DBLP]


  43. A radix-10 SRT divider based on alternative BCD codings. [Citation Graph (, )][DBLP]


  44. Hardware design of a Binary Integer Decimal-based floating-point adder. [Citation Graph (, )][DBLP]


  45. A parallel IEEE P754 decimal floating-point multiplier. [Citation Graph (, )][DBLP]


  46. Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier. [Citation Graph (, )][DBLP]


  47. Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence. [Citation Graph (, )][DBLP]


  48. Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. [Citation Graph (, )][DBLP]


  49. Improving the reliability of on-chip data caches under process variations. [Citation Graph (, )][DBLP]


  50. Prioritizing verification via value-based correctness criticality. [Citation Graph (, )][DBLP]


  51. Memory based computation using embedded cache for processor yield and reliability improvement. [Citation Graph (, )][DBLP]


  52. Accurate modeling and fault simulation of Byzantine resistive bridges. [Citation Graph (, )][DBLP]


  53. Negative-skewed shadow registers for at-speed delay variation characterization. [Citation Graph (, )][DBLP]


  54. An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. [Citation Graph (, )][DBLP]


  55. Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs. [Citation Graph (, )][DBLP]


  56. Modeling soft error effects considering process variations. [Citation Graph (, )][DBLP]


  57. An automated runtime power-gating scheme. [Citation Graph (, )][DBLP]


  58. A power gating scheme for ground bounce reduction during mode transition. [Citation Graph (, )][DBLP]


  59. Dynamically compressible context architecture for low power coarse-grained reconfigurable array. [Citation Graph (, )][DBLP]


  60. Post-layout comparison of high performance 64b static adders in energy-delay space. [Citation Graph (, )][DBLP]


  61. CAP: Criticality analysis for power-efficient speculative multithreading. [Citation Graph (, )][DBLP]


  62. Power-aware mapping for reconfigurable NoC architectures. [Citation Graph (, )][DBLP]


  63. LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. [Citation Graph (, )][DBLP]


  64. Power efficient register file update approach for embedded processors. [Citation Graph (, )][DBLP]


  65. A technique for selecting CMOS transistor orders. [Citation Graph (, )][DBLP]


  66. Algorithms to simplify multi-clock/edge timing constraints. [Citation Graph (, )][DBLP]


  67. An efficient gate delay model for VLSI design. [Citation Graph (, )][DBLP]


  68. Fast power network analysis with multiple clock domains. [Citation Graph (, )][DBLP]


  69. Statistical simulation of chip multiprocessors running multi-program workloads. [Citation Graph (, )][DBLP]


  70. Combining cluster sampling with single pass methods for efficient sampling regimen design. [Citation Graph (, )][DBLP]


  71. A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems. [Citation Graph (, )][DBLP]


  72. Limits on voltage scaling for caches utilizing fault tolerant techniques. [Citation Graph (, )][DBLP]


  73. VOSCH: Voltage scaled cache hierarchies. [Citation Graph (, )][DBLP]


  74. Exploiting eDRAM bandwidth with data prefetching: simulation and measurements. [Citation Graph (, )][DBLP]


  75. Digital calibration of RF transceivers for I-Q imbalances and nonlinearity. [Citation Graph (, )][DBLP]


  76. Fault-based alternate test of RF components. [Citation Graph (, )][DBLP]


  77. Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. [Citation Graph (, )][DBLP]


  78. A Study on self-timed asynchronous subthreshold logic. [Citation Graph (, )][DBLP]


  79. SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. [Citation Graph (, )][DBLP]


  80. Passive compensation for high performance inter-chip communication. [Citation Graph (, )][DBLP]


  81. Transparent mode flip-flops for collapsible pipelines. [Citation Graph (, )][DBLP]


  82. CMOS logic design with independent-gate FinFETs. [Citation Graph (, )][DBLP]


  83. Distributed voting for fault-tolerant nanoscale systems. [Citation Graph (, )][DBLP]


  84. Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits. [Citation Graph (, )][DBLP]


  85. VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication. [Citation Graph (, )][DBLP]


  86. Register binding guided by the size of variables. [Citation Graph (, )][DBLP]


  87. Power variations of multi-port routers in an application-specific NoC design : A case study. [Citation Graph (, )][DBLP]


  88. System level power estimation methodology with H.264 decoder prediction IP case study. [Citation Graph (, )][DBLP]


  89. A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs. [Citation Graph (, )][DBLP]


  90. Power reduction of chip multi-processors using shared resource control cooperating with DVFS. [Citation Graph (, )][DBLP]


  91. Effective Dynamic Thermal Management for MPEG-4 decoding. [Citation Graph (, )][DBLP]


  92. Priority-monotonic energy management for real-time systems with reliability requirements. [Citation Graph (, )][DBLP]


  93. Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002