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Conferences in DBLP

International Conference on Computer Design (ICCD) (iccd)
2008 (conf/iccd/2008)


  1. Fault tolerant Four-State Logic by using Self-Healing Cells. [Citation Graph (, )][DBLP]


  2. Probabilistic error propagation in logic circuits using the Boolean difference calculus. [Citation Graph (, )][DBLP]


  3. A novel, highly SEU tolerant digital circuit design approach. [Citation Graph (, )][DBLP]


  4. Power-state-aware buffered tree construction. [Citation Graph (, )][DBLP]


  5. A parallel Steiner tree heuristic for macro cell routing. [Citation Graph (, )][DBLP]


  6. Configurable rectilinear Steiner tree construction for SoC and nano technologies. [Citation Graph (, )][DBLP]


  7. Improving SAT-based Combinational Equivalence Checking through circuit preprocessing. [Citation Graph (, )][DBLP]


  8. Ant Colony Optimization directed program abstraction for software bounded model checking. [Citation Graph (, )][DBLP]


  9. Propositional approximations for bounded model checking of partial circuit designs. [Citation Graph (, )][DBLP]


  10. Energy-precision tradeoffs in mobile Graphics Processing Units. [Citation Graph (, )][DBLP]


  11. Dynamically reconfigurable soft output MIMO detector. [Citation Graph (, )][DBLP]


  12. Applying speculation techniques to implement functional units. [Citation Graph (, )][DBLP]


  13. Accelerating search and recognition with a TCAM functional unit. [Citation Graph (, )][DBLP]


  14. Improved combined binary/decimal fixed-point multipliers. [Citation Graph (, )][DBLP]


  15. Architecture implementation of an improved decimal CORDIC method. [Citation Graph (, )][DBLP]


  16. A study of reliability issues in clock distribution networks. [Citation Graph (, )][DBLP]


  17. Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations. [Citation Graph (, )][DBLP]


  18. Custom rotary clock router. [Citation Graph (, )][DBLP]


  19. Safe clocking register assignment in datapath synthesis. [Citation Graph (, )][DBLP]


  20. Gate planning during placement for gated clock network. [Citation Graph (, )][DBLP]


  21. Near-optimal oblivious routing on three-dimensional mesh networks. [Citation Graph (, )][DBLP]


  22. Design of application-specific 3D Networks-on-Chip architectures. [Citation Graph (, )][DBLP]


  23. Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic. [Citation Graph (, )][DBLP]


  24. A resource efficient content inspection system for next generation Smart NICs. [Citation Graph (, )][DBLP]


  25. Contention-aware application mapping for Network-on-Chip communication architectures. [Citation Graph (, )][DBLP]


  26. Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities. [Citation Graph (, )][DBLP]


  27. Adaptive SRAM memory for low power and high yield. [Citation Graph (, )][DBLP]


  28. On-chip high performance signaling using passive compensation. [Citation Graph (, )][DBLP]


  29. A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. [Citation Graph (, )][DBLP]


  30. Characterization and design of sequential circuit elements to combat soft error. [Citation Graph (, )][DBLP]


  31. Comparative analysis of NBTI effects on low power and high performance flip-flops. [Citation Graph (, )][DBLP]


  32. In-field NoC-based SoC testing with distributed test vector storage. [Citation Graph (, )][DBLP]


  33. Test-access mechanism optimization for core-based three-dimensional SOCs. [Citation Graph (, )][DBLP]


  34. Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. [Citation Graph (, )][DBLP]


  35. Dynamic test scheduling for analog circuits for improved test quality. [Citation Graph (, )][DBLP]


  36. Test cost minimization through adaptive test development. [Citation Graph (, )][DBLP]


  37. Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA. [Citation Graph (, )][DBLP]


  38. A high-performance parallel CAVLC encoder on a fine-grained many-core system. [Citation Graph (, )][DBLP]


  39. Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. [Citation Graph (, )][DBLP]


  40. Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs. [Citation Graph (, )][DBLP]


  41. Application Specific Instruction set processor specialized for block motion estimation. [Citation Graph (, )][DBLP]


  42. Prototyping a hybrid main memory using a virtual machine monitor. [Citation Graph (, )][DBLP]


  43. Variation-aware thermal characterization and management of multi-core architectures. [Citation Graph (, )][DBLP]


  44. Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective. [Citation Graph (, )][DBLP]


  45. Analysis and minimization of practical energy in 45nm subthreshold logic circuits. [Citation Graph (, )][DBLP]


  46. Power-aware soft error hardening via selective voltage scaling. [Citation Graph (, )][DBLP]


  47. Reversi: Post-silicon validation system for modern microprocessors. [Citation Graph (, )][DBLP]


  48. Digital filter synthesis considering multiple adder graphs for a coefficient. [Citation Graph (, )][DBLP]


  49. A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications. [Citation Graph (, )][DBLP]


  50. Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264. [Citation Graph (, )][DBLP]


  51. Highly reliable A/D converter using analog voting. [Citation Graph (, )][DBLP]


  52. Hierarchical simulation-based verification of Anton, a special-purpose parallel machine. [Citation Graph (, )][DBLP]


  53. Post-silicon verification for cache coherence. [Citation Graph (, )][DBLP]


  54. Acquiring an exhaustive, continuous and real-time trace from SoCs. [Citation Graph (, )][DBLP]


  55. CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. [Citation Graph (, )][DBLP]


  56. Exploiting spare resources of in-order SMT processors executing hard real-time threads. [Citation Graph (, )][DBLP]


  57. Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design. [Citation Graph (, )][DBLP]


  58. A simple latency tolerant processor. [Citation Graph (, )][DBLP]


  59. Low-cost open-page prefetch scheduling in chip multiprocessors. [Citation Graph (, )][DBLP]


  60. Simulation points for SPEC CPU 2006. [Citation Graph (, )][DBLP]


  61. Synthesis of parallel prefix adders considering switching activities. [Citation Graph (, )][DBLP]


  62. Conversion driven design of binary to mixed radix circuits. [Citation Graph (, )][DBLP]


  63. Systematic design of high-radix Montgomery multipliers for RSA processors. [Citation Graph (, )][DBLP]


  64. An improved micro-architecture for function approximation using piecewise quadratic interpolation. [Citation Graph (, )][DBLP]


  65. A floating-point fused dot-product unit. [Citation Graph (, )][DBLP]


  66. Chip level thermal profile estimation using on-chip temperature sensors. [Citation Graph (, )][DBLP]


  67. Early stage FPGA interconnect leakage power estimation. [Citation Graph (, )][DBLP]


  68. Modeling and analysis of non-rectangular transistors caused by lithographic distortions. [Citation Graph (, )][DBLP]


  69. A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions. [Citation Graph (, )][DBLP]


  70. Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. [Citation Graph (, )][DBLP]


  71. Frequency and voltage planning for multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]


  72. Understanding performance, power and energy behavior in asymmetric multiprocessors. [Citation Graph (, )][DBLP]


  73. Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. [Citation Graph (, )][DBLP]


  74. The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks. [Citation Graph (, )][DBLP]


  75. Design and evaluation of an optical CPU-DRAM interconnect. [Citation Graph (, )][DBLP]


  76. Leveraging speculative architectures for run-time program validation. [Citation Graph (, )][DBLP]


  77. Bridging the gap between nanomagnetic devices and circuits. [Citation Graph (, )][DBLP]


  78. Techniques for increasing effective data bandwidth. [Citation Graph (, )][DBLP]


  79. RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache. [Citation Graph (, )][DBLP]


  80. Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. [Citation Graph (, )][DBLP]


  81. Timing analysis considering IR drop waveforms in power gating designs. [Citation Graph (, )][DBLP]


  82. A dynamic accuracy-refinement approach to timing-driven technology mapping. [Citation Graph (, )][DBLP]


  83. Modeling and reduction of complex timing constraints in high performance digital circuits. [Citation Graph (, )][DBLP]


  84. SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. [Citation Graph (, )][DBLP]


  85. Is there always performance overhead for regular fabric? [Citation Graph (, )][DBLP]


  86. Adaptive techniques for leakage power management in L2 cache peripheral circuits. [Citation Graph (, )][DBLP]


  87. Energy-aware opcode design. [Citation Graph (, )][DBLP]


  88. Making register file resistant to power analysis attacks. [Citation Graph (, )][DBLP]


  89. Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads. [Citation Graph (, )][DBLP]


  90. Suitable cache organizations for a novel biomedical implant processor. [Citation Graph (, )][DBLP]


  91. Issue system protection mechanisms. [Citation Graph (, )][DBLP]


  92. Power switch characterization for fine-grained dynamic voltage scaling. [Citation Graph (, )][DBLP]


  93. A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]


  94. Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. [Citation Graph (, )][DBLP]


  95. Energy-delay tradeoffs in 32-bit static shifter designs. [Citation Graph (, )][DBLP]


  96. Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems. [Citation Graph (, )][DBLP]


  97. Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits. [Citation Graph (, )][DBLP]


  98. Router and cell library co-development for improving redundant via insertion at pins. [Citation Graph (, )][DBLP]


  99. ECO-Map: Technology remapping for post-mask ECO using simulated annealing. [Citation Graph (, )][DBLP]


  100. Global bus route optimization with application to microarchitectural design exploration. [Citation Graph (, )][DBLP]


  101. Fast arbiters for on-chip network switches. [Citation Graph (, )][DBLP]


  102. Re-examining cache replacement policies. [Citation Graph (, )][DBLP]


  103. Two dimensional highly associative level-two cache design. [Citation Graph (, )][DBLP]


  104. Exploiting producer patterns and L2 cache for timely dependence-based prefetching. [Citation Graph (, )][DBLP]


  105. Ring data location prediction scheme for Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP]


  106. ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002