Conferences in DBLP
Design and performance of a general class of interconnection networks. [Citation Graph (, )][DBLP ] Augmented and pruned n log n multistaged networks: topology and performance. [Citation Graph (, )][DBLP ] Performance of self-routing shuffle-exchange interconnection network in SIMD processors. [Citation Graph (, )][DBLP ] SP2I interconnection network and extension of the iteration method of automatic vector-routing. [Citation Graph (, )][DBLP ] Distributed circuit switching starnet. [Citation Graph (, )][DBLP ] Comparative study of the exploitation of different levels of parallelism on different parallel architectures. [Citation Graph (, )][DBLP ] A mesh coloring method for efficient MIMD processing in finite element problems. [Citation Graph (, )][DBLP ] An efficient parallel block conjugate method for linear equations. [Citation Graph (, )][DBLP ] A multi-color SOR method for parallel computation. [Citation Graph (, )][DBLP ] A parallel algorithm for finding the roots of a polynomial. [Citation Graph (, )][DBLP ] Optimizing the FACR Poisson-solver on parallel computers. [Citation Graph (, )][DBLP ] Parallel Poisson and biharmonic solvers implemented on the EGPA multiprocessor. [Citation Graph (, )][DBLP ] Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor. [Citation Graph (, )][DBLP ] Optimal implementation of signal flow graphs on synchronous multiprocessors. [Citation Graph (, )][DBLP ] A test strategy for packet switching networks. [Citation Graph (, )][DBLP ] On fault-diagnosis of some multistage networks. [Citation Graph (, )][DBLP ] Fault tolerance analysis of several interconnection networks. [Citation Graph (, )][DBLP ] A fault-tolerant connecting network for multiprocessing systems. [Citation Graph (, )][DBLP ] A fault tolerant interconnection network using error correcting codes. [Citation Graph (, )][DBLP ] DDSP - A data flow computer for signal processing. [Citation Graph (, )][DBLP ] Summary of a hybrid data flow system. [Citation Graph (, )][DBLP ] Function sharing in a static data flow machine. [Citation Graph (, )][DBLP ] SERFRE: A general-purpose multi-processor reduction machine. [Citation Graph (, )][DBLP ] A language for specification and programming of reconfigurable parallel computation structures. [Citation Graph (, )][DBLP ] Algebra of events: a model for parallel and real time systems. [Citation Graph (, )][DBLP ] Resource expressions for applicative languages. [Citation Graph (, )][DBLP ] Parallel implementation of functional languages. [Citation Graph (, )][DBLP ] Parallel generation of the postfix form. [Citation Graph (, )][DBLP ] A parallel matching algorithm for convex bipartite graphs. [Citation Graph (, )][DBLP ] Significance of problem solving parameters on the performance of combinatorial algorithms on multi-computer parallel architectures. [Citation Graph (, )][DBLP ] NOVAC: a non-tree variable tree for combinatorial computing. [Citation Graph (, )][DBLP ] Results in parallel searching, merging, and sorting. [Citation Graph (, )][DBLP ] On computing weak transitive closure on O(log N) expected random parallel time. [Citation Graph (, )][DBLP ] Alternative approaches to multiprocessor garbage collection. [Citation Graph (, )][DBLP ] Concurrent disk accessing for partial match retrieval. [Citation Graph (, )][DBLP ] Algorithms for replace-add based paracomputers. [Citation Graph (, )][DBLP ] Constructing parallel programs and their termination proof. [Citation Graph (, )][DBLP ] Multiple pipeline scheduling in vector supercomputers. [Citation Graph (, )][DBLP ] Performance evaluation of three automatic vectorizer packages. [Citation Graph (, )][DBLP ] Results of parallel processing a large scientific problem on a commercially available multiple-processor computer system. [Citation Graph (, )][DBLP ] Kernel-control tailoring of sequential programs for parallel execution. [Citation Graph (, )][DBLP ] A performance model for instruction prefetch in pipelined instruction units. [Citation Graph (, )][DBLP ] Programming techniques on the LUCAS associative array computer. [Citation Graph (, )][DBLP ] Wafer scale integration of Configurable, Highly Parallel (CHiP) processors. [Citation Graph (, )][DBLP ] Testing coordination for "homogeneous" parallel algorithms. [Citation Graph (, )][DBLP ] Efficient parallel algorithms for processor arrays. [Citation Graph (, )][DBLP ] MPP VLSI multiprocessor integrated circuit design. [Citation Graph (, )][DBLP ] Parallel simulation by means of a prescheduled MIMD-system featuring synchronous pipeline processors. [Citation Graph (, )][DBLP ] Pipelining array computations for MIMD parallelism: a function specification. [Citation Graph (, )][DBLP ] Combining partial results in an MIMD computer. [Citation Graph (, )][DBLP ] An approximate analytical model for asynchronous processes in multiprocessors. [Citation Graph (, )][DBLP ] The automated design of task-specific parallel processing architectures. [Citation Graph (, )][DBLP ] A bit-sequential multi-operand inner product processor. [Citation Graph (, )][DBLP ] A digit online arithmetic simulator. [Citation Graph (, )][DBLP ] A parallel architecture for acoustic processing in speech understanding. [Citation Graph (, )][DBLP ] A novel approach to parallel processing cryptosystem. [Citation Graph (, )][DBLP ] A parallel/pipeline processor for fast exponentiation. [Citation Graph (, )][DBLP ] Island universes: distributing a single-user operating system. [Citation Graph (, )][DBLP ] A varied strategy programmable arbiter. [Citation Graph (, )][DBLP ] Using write back cache to improve performance of multi-user multiprocessors. [Citation Graph (, )][DBLP ] Coherence problem in a multi-cache system. [Citation Graph (, )][DBLP ] Constrained expression and the analysis of designs for dynamically-structured distributed systems. [Citation Graph (, )][DBLP ] Analysis of a splitted-bus distributed multiprocessor system. [Citation Graph (, )][DBLP ] Logic Programming on ZMOB: A Highly Parallel Machine. [Citation Graph (, )][DBLP ] System Architecture of a Reconfigurable Multimicroprocessor Research System. [Citation Graph (, )][DBLP ] Design and simulation of an MC68000-based multi-microprocessor system. [Citation Graph (, )][DBLP ] Analysis of the PASM control system memory hierarchy. [Citation Graph (, )][DBLP ] 