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Conferences in DBLP

International Conference on Supercomputing (ICS) (ics)
2009 (conf/ics/2009)

  1. A european perspective on supercomputing. [Citation Graph (, )][DBLP]

  2. The roadrunner project and the importance of energy efficiency on the road to exascale computing. [Citation Graph (, )][DBLP]

  3. Computing outside the box. [Citation Graph (, )][DBLP]

  4. Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine. [Citation Graph (, )][DBLP]

  5. High-performance regular expression scanning on the Cell/B.E. processor. [Citation Graph (, )][DBLP]

  6. Computer generation of fast fourier transforms for the cell broadband engine. [Citation Graph (, )][DBLP]

  7. DBDB: optimizing DMATransfer for the cell be architecture. [Citation Graph (, )][DBLP]

  8. Zero-content augmented caches. [Citation Graph (, )][DBLP]

  9. Dynamic cache clustering for chip multiprocessors. [Citation Graph (, )][DBLP]

  10. Less reused filter: improving l2 cache performance via filtering less reused lines. [Citation Graph (, )][DBLP]

  11. Divide-and-conquer: a bubble replacement for low level caches. [Citation Graph (, )][DBLP]

  12. OhHelp: a scalable domain-decomposing dynamic load balancing for particle-in-cell simulations. [Citation Graph (, )][DBLP]

  13. Pattern-based sparse matrix representation for memory-efficient SMVM kernels. [Citation Graph (, )][DBLP]

  14. Dynamic topology aware load balancing algorithms for molecular dynamics applications. [Citation Graph (, )][DBLP]

  15. Fast memory snapshot for concurrent programmingwithout synchronization. [Citation Graph (, )][DBLP]

  16. QuakeTM: parallelizing a complex sequential application using transactional memory. [Citation Graph (, )][DBLP]

  17. Refereeing conflicts in hardware transactional memory. [Citation Graph (, )][DBLP]

  18. Parametric multi-level tiling of imperfectly nested loops. [Citation Graph (, )][DBLP]

  19. Dynamic parallelization of single-threaded binary programs using speculative slicing. [Citation Graph (, )][DBLP]

  20. Synchronization optimizations for efficient execution on multi-cores. [Citation Graph (, )][DBLP]

  21. Chunking parallel loops in the presence of synchronization. [Citation Graph (, )][DBLP]

  22. Efficient high performance collective communication for the cell blade. [Citation Graph (, )][DBLP]

  23. Practice of parallelizing network applications on multi-core architectures. [Citation Graph (, )][DBLP]

  24. Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design. [Citation Graph (, )][DBLP]

  25. Virtualization polling engine (VPE): using dedicated CPU cores to accelerate I/O virtualization. [Citation Graph (, )][DBLP]

  26. Fast and scalable list ranking on the GPU. [Citation Graph (, )][DBLP]

  27. Tuned and wildly asynchronous stencil kernels for hybrid CPU/GPU systems. [Citation Graph (, )][DBLP]

  28. Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs. [Citation Graph (, )][DBLP]

  29. Creating artificial global history to improve branch prediction accuracy. [Citation Graph (, )][DBLP]

  30. Exploring pattern-aware routing in generalized fat tree networks. [Citation Graph (, )][DBLP]

  31. Understanding the interconnection network of SpiNNaker. [Citation Graph (, )][DBLP]

  32. A graph based approach for MPI deadlock detection. [Citation Graph (, )][DBLP]

  33. Maximizing MPI point-to-point communication performance on RDMA-enabled clusters with customized protocols. [Citation Graph (, )][DBLP]

  34. MPI-aware compiler optimizations for improving communication-computation overlap. [Citation Graph (, )][DBLP]

  35. Evaluating high performance communication: a power perspective. [Citation Graph (, )][DBLP]

  36. FTL design exploration in reconfigurable high-performance SSD for server applications. [Citation Graph (, )][DBLP]

  37. /scratch as a cache: rethinking HPC center scratch storage. [Citation Graph (, )][DBLP]

  38. P-Code: a new RAID-6 code with optimal properties. [Citation Graph (, )][DBLP]

  39. R-ADMAD: high reliability provision for large-scale de-duplication archival storage systems. [Citation Graph (, )][DBLP]

  40. Single-particle 3d reconstruction from cryo-electron microscopy images on GPU. [Citation Graph (, )][DBLP]

  41. How GPUs can outperform ASICs for fast LDPC decoding. [Citation Graph (, )][DBLP]

  42. A translation system for enabling data mining applications on GPUs. [Citation Graph (, )][DBLP]

  43. Combining thread level speculation helper threads and runahead execution. [Citation Graph (, )][DBLP]

  44. Limited early value communication to improve performance of transactional memory. [Citation Graph (, )][DBLP]

  45. EpiFast: a fast algorithm for large scale realistic epidemic simulations on distributed memory systems. [Citation Graph (, )][DBLP]

  46. Using many-core hardware to correlate radio astronomy signals. [Citation Graph (, )][DBLP]

  47. A parallel levenberg-marquardt algorithm. [Citation Graph (, )][DBLP]

  48. Adagio: making DVS practical for complex HPC applications. [Citation Graph (, )][DBLP]

  49. A comprehensive power-performance model for NoCs with multi-flit channel buffers. [Citation Graph (, )][DBLP]

  50. Rate-based QoS techniques for cache/memory in CMP platforms. [Citation Graph (, )][DBLP]

  51. MPI collective communications on the blue gene/p supercomputer: algorithms and optimizations. [Citation Graph (, )][DBLP]

  52. TransMetric: architecture independent workload characterization for transactional memory benchmarks. [Citation Graph (, )][DBLP]

  53. Cancellation of loads that return zero using zero-value caches. [Citation Graph (, )][DBLP]

  54. Auto-vectorization through code generation for stream processing applications. [Citation Graph (, )][DBLP]

  55. Subdomain communication to increase scalability in large-scale scientific applications. [Citation Graph (, )][DBLP]

  56. Access map pattern matching for data cache prefetch. [Citation Graph (, )][DBLP]

  57. Prediction-based power estimation and scheduling for CMPs. [Citation Graph (, )][DBLP]

  58. Design of a novel SIMD architecture by fusing operations and registers. [Citation Graph (, )][DBLP]

  59. Thrifty interconnection network for HPC systems. [Citation Graph (, )][DBLP]

  60. Performance modeling for DFT algorithms in FFTW. [Citation Graph (, )][DBLP]

  61. PARSEC: hardware profiling of emerging workloads for CMP design. [Citation Graph (, )][DBLP]

  62. Approximate kernel matrix computation on GPUs forlarge scale learning applications. [Citation Graph (, )][DBLP]

  63. Dynamic task set partitioning based on balancing memory requirements to reduce power consumption. [Citation Graph (, )][DBLP]

  64. High-performance CUDA kernel execution on FPGAs. [Citation Graph (, )][DBLP]

  65. Load balancing using work-stealing for pipeline parallelism in emerging applications. [Citation Graph (, )][DBLP]

  66. Prefetch optimizations on large-scale applications via parameter value prediction. [Citation Graph (, )][DBLP]

  67. Designing multi-socket systems using silicon photonics. [Citation Graph (, )][DBLP]

  68. An infrastructure for scalable and portable parallel programs for computational chemistry. [Citation Graph (, )][DBLP]

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