Conferences in DBLP
Michael Wolfe How compilers and tools differ for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Laura Pozzi , Paolo Ienne Exploiting pipelining to relax register-file port constraints of instruction-set extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Sami Yehia , Nathan Clark , Scott A. Mahlke , Krisztián Flautner Exploring the design space of LUT-based transparent accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Ray C. C. Cheung , Dong-U Lee , Oskar Mencer , Wayne Luk , Peter Y. K. Cheung Automating custom-precision function evaluation for embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Rony Ghattas , Alexander G. Dean Energy management for commodity short-bit-width microcontrollers. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Zhang , Xiaotong Zhuang , Santosh Pande , Wenke Lee Anomalous path detection with hardware support. [Citation Graph (0, 0)][DBLP ] Conf ] Milena Milenkovic , Aleksandar Milenkovic , Emil Jovanov Hardware support for code integrity in embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Simpson , Bhuvan Middha , Rajeev Barua Segment protection for embedded systems using run-time checks. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Coburn , Srivaths Ravi , Anand Raghunathan , Srimat T. Chakradhar SECA: security-enhanced communication architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Aviral Shrivastava , Ilya Issenin , Nikil Dutt Compilation techniques for energy reduction in horizontally partitioned cache architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Montserrat Ros , Peter Sutton A post-compilation register reassignment technique for improving hamming distance code compression. [Citation Graph (0, 0)][DBLP ] Conf ] Guangyu Chen , Mahmut T. Kandemir Verifiable annotations for embedded java environments. [Citation Graph (0, 0)][DBLP ] Conf ] Nghi Nguyen , Angel Dominguez , Rajeev Barua Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. [Citation Graph (0, 0)][DBLP ] Conf ] Sitij Agrawal , William Thies , Saman P. Amarasinghe Optimizing stream programs using linear state space analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Feihui Li , Guangyu Chen , Mahmut T. Kandemir , Mary Jane Irwin Compiler-directed proactive power management for networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Ali Ghodrat , Tony Givargis , Alexandru Nicolau Equivalence checking of arithmetic expressions using fast evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunok Oh , Nikil D. Dutt , Soonhoi Ha Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco J. Cazorla , Peter M. W. Knijnenburg , Rizos Sakellariou , Enrique Fernández , Alex Ramírez , Mateo Valero Architectural support for real-time task scheduling in SMT processors. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Valentin Gheorghita , Twan Basten , Henk Corporaal Intra-task scenario-aware voltage scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] A. Goel , C. Mani Krishna , Israel Koren Energy aware kernel for hard real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bhuvan Middha , Matthew Simpson , Rajeev Barua MTSS: multi task stack sharing for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Yiannacouras , Jonathan Rose , J. Gregory Steffan The microarchitecture of FPGA-based soft processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ali El-Haj-Mahmoud , Ahmed S. Al-Zawawi , Aravindh Anantaraman , Eric Rotenberg Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Jan Lukoschus , Marian Boldt , Michael Harder , Reinhard von Hanxleden An Esterel processor with full preemption support and its worst case reaction time analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Y. Yeh , Glenn Reinman Fast and fair: data-stream quality of service. [Citation Graph (0, 0)][DBLP ] Conf ] Leyla Nazhandali , Michael Minuth , Bo Zhai , Javin Olson , Todd M. Austin , David Blaauw A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunseok Lee , Trevor N. Mudge A dual-processor solution for the MAC layer of a software defined radio terminal. [Citation Graph (0, 0)][DBLP ] Conf ] Suman Mamidi , Emily R. Blem , Michael J. Schulte , C. John Glossner , Daniel Iancu , Andrei Iancu , Mayan Moudgill , Sanjay Jinturkar Instruction set extensions for software defined radio on a multithreaded processor. [Citation Graph (0, 0)][DBLP ] Conf ] Vassos Soteriou , Noel Eisley , Li-Shiuan Peh Software-directed power-aware interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Siddhartha Shivshankar , Sunil Vangara , Alexander G. Dean Balancing register pressure and context-switching delays in ASTI systems. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew D. Roper , Ronald A. Olsson Developing embedded multi-threaded applications with CATAPULTS, a domain-specific language for generating thread schedulers. [Citation Graph (0, 0)][DBLP ] Conf ] Roshan G. Ragel , Sri Parameswaran , Sayed Mohammad Kia Micro embedded monitoring for security in application specific instruction-set processors. [Citation Graph (0, 0)][DBLP ] Conf ] 