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Conferences in DBLP

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) (cases)
2005 (conf/cases/2005)

  1. Michael Wolfe
    How compilers and tools differ for embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:1- [Conf]
  2. Laura Pozzi, Paolo Ienne
    Exploiting pipelining to relax register-file port constraints of instruction-set extensions. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:2-10 [Conf]
  3. Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner
    Exploring the design space of LUT-based transparent accelerators. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:11-21 [Conf]
  4. Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Automating custom-precision function evaluation for embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:22-31 [Conf]
  5. Rony Ghattas, Alexander G. Dean
    Energy management for commodity short-bit-width microcontrollers. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:32-42 [Conf]
  6. Tao Zhang, Xiaotong Zhuang, Santosh Pande, Wenke Lee
    Anomalous path detection with hardware support. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:43-54 [Conf]
  7. Milena Milenkovic, Aleksandar Milenkovic, Emil Jovanov
    Hardware support for code integrity in embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:55-65 [Conf]
  8. Matthew Simpson, Bhuvan Middha, Rajeev Barua
    Segment protection for embedded systems using run-time checks. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:66-77 [Conf]
  9. Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    SECA: security-enhanced communication architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:78-89 [Conf]
  10. Aviral Shrivastava, Ilya Issenin, Nikil Dutt
    Compilation techniques for energy reduction in horizontally partitioned cache architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:90-96 [Conf]
  11. Montserrat Ros, Peter Sutton
    A post-compilation register reassignment technique for improving hamming distance code compression. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:97-104 [Conf]
  12. Guangyu Chen, Mahmut T. Kandemir
    Verifiable annotations for embedded java environments. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:105-114 [Conf]
  13. Nghi Nguyen, Angel Dominguez, Rajeev Barua
    Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:115-125 [Conf]
  14. Sitij Agrawal, William Thies, Saman P. Amarasinghe
    Optimizing stream programs using linear state space analysis. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:126-136 [Conf]
  15. Feihui Li, Guangyu Chen, Mahmut T. Kandemir, Mary Jane Irwin
    Compiler-directed proactive power management for networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:137-146 [Conf]
  16. Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau
    Equivalence checking of arithmetic expressions using fast evaluation. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:147-156 [Conf]
  17. Hyunok Oh, Nikil D. Dutt, Soonhoi Ha
    Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:157-165 [Conf]
  18. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Architectural support for real-time task scheduling in SMT processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:166-176 [Conf]
  19. Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal
    Intra-task scenario-aware voltage scheduling. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:177-184 [Conf]
  20. A. Goel, C. Mani Krishna, Israel Koren
    Energy aware kernel for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:185-190 [Conf]
  21. Bhuvan Middha, Matthew Simpson, Rajeev Barua
    MTSS: multi task stack sharing for embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:191-201 [Conf]
  22. Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan
    The microarchitecture of FPGA-based soft processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:202-212 [Conf]
  23. Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg
    Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:213-224 [Conf]
  24. Xin Li, Jan Lukoschus, Marian Boldt, Michael Harder, Reinhard von Hanxleden
    An Esterel processor with full preemption support and its worst case reaction time analysis. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:225-236 [Conf]
  25. Thomas Y. Yeh, Glenn Reinman
    Fast and fair: data-stream quality of service. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:237-248 [Conf]
  26. Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw
    A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:249-256 [Conf]
  27. Hyunseok Lee, Trevor N. Mudge
    A dual-processor solution for the MAC layer of a software defined radio terminal. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:257-265 [Conf]
  28. Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar
    Instruction set extensions for software defined radio on a multithreaded processor. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:266-273 [Conf]
  29. Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
    Software-directed power-aware interconnection networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:274-285 [Conf]
  30. Siddhartha Shivshankar, Sunil Vangara, Alexander G. Dean
    Balancing register pressure and context-switching delays in ASTI systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:286-294 [Conf]
  31. Matthew D. Roper, Ronald A. Olsson
    Developing embedded multi-threaded applications with CATAPULTS, a domain-specific language for generating thread schedulers. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:295-303 [Conf]
  32. Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia
    Micro embedded monitoring for security in application specific instruction-set processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:304-314 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002