Conferences in DBLP
Jinson Koppanalil , Prakash Ramrakhyani , Sameer Desai , Anu Vaidyanathan , Eric Rotenberg A case for dynamic pipeline scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Jack Liu , Fred C. Chow A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Genssler , Alexander Christoph , Michael Winter , Oscar Nierstrasz , Stéphane Ducasse , Roel Wuyts , Gabriela Arévalo , Bastiaan Schönhage , Peter O. Müller , Christian Stich Components for embedded software: the PECOS approach. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Fischer , Jürgen Teich , Michael Thies , Ralph Weper Efficient architecture/compiler co-exploration for ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund Sivaraman , Shail Aditya Cycle-time aware architecture synthesis of custom hardware accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Mladen Nikitovic , Mats Brorsson An adaptive chip-multiprocessor architecture for future mobile terminals. [Citation Graph (0, 0)][DBLP ] Conf ] Amol Bakshi , Jingzhao Ou , Viktor K. Prasanna Towards automatic synthesis of a class of application-specific sensor networks. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Ward , Neil C. Audsley Hardware implementation of the Ravenscar Ada tasking profile. [Citation Graph (0, 0)][DBLP ] Conf ] Bengu Li , Rajiv Gupta Bit section instruction set extension of ARM for embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hillery C. Hunter , Wen-mei W. Hwu Code coverage and input variability: effects on architecture and compiler research. [Citation Graph (0, 0)][DBLP ] Conf ] Jayaprakash Pisharath , Alok N. Choudhary An integrated approach to reducing power dissipation in memory hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] Afzal Malik , Bill Moyer , Roger Zhou Embedded cache architecture with programmable write buffer support for power and performance flexibility. [Citation Graph (0, 0)][DBLP ] Conf ] Gokhan Memik , William H. Mangione-Smith Increasing power efficiency of multi-core network processors through data filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Esther Salamí , Jesús Corbal , Carlos Álvarez , Mateo Valero Cost effective memory disambiguation for multimedia codes. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Ismail Kadayif , Alok N. Choudhary , Joseph Zambreno Optimizing inter-nest data locality. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Zhang , Santosh Pande , André L. M. dos Santos , Franz Josef Bruecklmayr Leakage-proof program partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Liang Kuo , Tien-Fu Chen Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijian Lu , Jason Hein , Marty Humphrey , Mircea R. Stan , John Lach , Kevin Skadron Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Ravindra Jejurikar , Rajesh K. Gupta Energy aware task scheduling with task synchronization for embedded real time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffry T. Russell , Margarida F. Jacome Scenario-based software characterization as a contingency to traditional program profiling. [Citation Graph (0, 0)][DBLP ] Conf ] Jinhwan Kim , Sungjoon Jung , Yunheung Paek , Gang-Ryung Uh Experience with a retargetable compiler for a commercial network processor. [Citation Graph (0, 0)][DBLP ] Conf ] Alex K. Jones , Debabrata Bagchi , Satrajit Pal , Xiaoyong Tang , Alok N. Choudhary , Prithviraj Banerjee PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Jiang Xu , Wayne Wolf Wave pipelining for application-specific networks-on-chips. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen W. Melvin , Yale N. Patt Handling of packet dependencies: a critical issue for highly parallel network processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbo Yang , Guang R. Gao , Clement Leung On achieving balanced power consumption in software pipelined loops. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Gatti , Andrea Acquaviva , Luca Benini , Bruno Riccò Low Power Control Techniques For TFT LCD Displays. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Park , Mani B. Srivastava Dynamic battery state aware approaches for improving battery utilization. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Bruni , Luca Benini , Bruno Riccò System lifetime extension by battery management: an experimental work. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Weissel , Frank Bellosa Process cruise control: event-driven clock scaling for dynamic power management. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Ben Chehida , Michel Auguin HW / SW partitioning approach for reconfigurable system design. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar An efficient technique for exploring register file size in ASIP synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Brisk , Adam Kaplan , Ryan Kastner , Majid Sarrafzadeh Instruction generation and regularity extraction for reconfigurable processors. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Menard , Daniel Chillet , François Charot , Olivier Sentieys Automatic floating-point to fixed-point conversion for DSP code generation. [Citation Graph (0, 0)][DBLP ] Conf ] Dae-Hwan Kim , Hyuk-Jae Lee Iterative procedural abstraction for code size reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Raya Leviathan , Amir Pnueli Validating software pipelining optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Sumant Kowshik , Dinakar Dhurjati , Vikram S. Adve Ensuring code safety without runtime checks for real-time control systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alwyn Goodloe , Michael McDougall , Carl A. Gunter , Rajeev Alur Predictable programs in barcodes. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Nilsson , Torbjörn Ekman , Klas Nilsson Real Java for real time - gain and pain. [Citation Graph (0, 0)][DBLP ] Conf ] 