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Conferences in DBLP

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) (cases)
2003 (conf/cases/2003)

  1. Joseph A. Fisher
    Moving from embedded systems to embedded computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:1- [Conf]
  2. Dorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks
    Vectorizing for a SIMdD DSP architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:2-11 [Conf]
  3. Bengu Li, Rajiv Gupta
    Simple offset assignment in presence of subword data. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:12-23 [Conf]
  4. V. Krishna Nandivada, Jens Palsberg
    Efficient spill code for SDRAM. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:24-31 [Conf]
  5. Andrei Terechko, Erwan Le Thenaff, Henk Corporaal
    Cluster assignment of global values for clustered VLIW processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:32-40 [Conf]
  6. Benjamin J. Welch, Shobhit O. Kanaujia, Adarsh Seetharam, Deepaksrivats Thirumalai, Alexander G. Dean
    Extending STI for demanding hard-real-time systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:41-50 [Conf]
  7. Andreas Ermedahl, Friedhelm Stappert, Jakob Engblom
    Clustered calculation of worst-case execution times. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:51-62 [Conf]
  8. Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman
    Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:63-72 [Conf]
  9. Juanjo Noguera, Rosa M. Badia
    System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:73-83 [Conf]
  10. Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder
    Reducing code size with echo instructions. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:84-94 [Conf]
  11. Montserrat Ros, Peter Sutton
    Compiler optimization and ordering effects on VLIW code compression. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:95-103 [Conf]
  12. Partha Biswas, Nikil D. Dutt
    Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:104-112 [Conf]
  13. Krishna V. Palem
    Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:113-116 [Conf]
  14. Ann Gordon-Ross, Frank Vahid
    Frequent loop detection using efficient non-intrusive on-chip hardware. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:117-124 [Conf]
  15. Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
    Increasing the number of effective registers in a low-power processor using a windowed register file. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:125-136 [Conf]
  16. David Goodwin, Darin Petkov
    Automatic generation of application specific processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:137-147 [Conf]
  17. Osvaldo Colavin, Davide Rizzo
    A scalable wide-issue clustered VLIW with a reconfigurable interconnect. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:148-158 [Conf]
  18. Hillery C. Hunter, Jaime H. Moreno
    A new look at exploiting data parallelism in embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:159-169 [Conf]
  19. Massimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli, Maurizio Peri, Saverio Pezzini
    Fault-tolerant platforms for automotive safety-critical applications. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:170-177 [Conf]
  20. Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
    Programming challenges in network processor deployment. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:178-187 [Conf]
  21. Ramnath Venugopalan, Prasanth Ganesan, Pushkin Peddabachagari, Alexander G. Dean, Frank Mueller, Mihail L. Sichitiu
    Encryption overhead in embedded systems and sensor network nodes: modeling and analysis. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:188-197 [Conf]
  22. Dino Oliva, Rainer Buchty, Nevin Heintze
    AES and the cryptonite crypto processor. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:198-209 [Conf]
  23. Binu K. Mathew, Al Davis, Zhen Fang
    A low-power accelerator for the SPHINX 3 speech recognition system. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:210-219 [Conf]
  24. Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
    Architectural optimizations for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:220-231 [Conf]
  25. Lin Zhong, Niraj K. Jha
    Graphical user interface energy characterization for handheld computers. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:232-242 [Conf]
  26. Sumit Mohanty, Viktor K. Prasanna
    A hierarchical approach for energy efficient application design using heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:243-254 [Conf]
  27. Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob
    A control-theoretic approach to dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:255-266 [Conf]
  28. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan
    Power efficient encoding techniques for off-chip data buses. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:267-275 [Conf]
  29. Sumesh Udayakumaran, Rajeev Barua
    Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:276-286 [Conf]
  30. Guilin Chen, Mahmut T. Kandemir, Hendra Saputra, Mary Jane Irwin
    Exploiting bank locality in multi-bank memories. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:287-297 [Conf]
  31. Alain Darte, Robert Schreiber, Gilles Villard
    Lattice-based memory allocation. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:298-308 [Conf]
  32. Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
    Performance, energy, and reliability tradeoffs in replicating hot cache lines. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:309-317 [Conf]
  33. Federico Angiolini, Luca Benini, Alberto Caprara
    Polynomial-time algorithm for on-chip scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:318-326 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002