Conferences in DBLP
Joseph A. Fisher Moving from embedded systems to embedded computing. [Citation Graph (0, 0)][DBLP ] Conf ] Dorit Naishlos , Marina Biberstein , Shay Ben-David , Ayal Zaks Vectorizing for a SIMdD DSP architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Bengu Li , Rajiv Gupta Simple offset assignment in presence of subword data. [Citation Graph (0, 0)][DBLP ] Conf ] V. Krishna Nandivada , Jens Palsberg Efficient spill code for SDRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Terechko , Erwan Le Thenaff , Henk Corporaal Cluster assignment of global values for clustered VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin J. Welch , Shobhit O. Kanaujia , Adarsh Seetharam , Deepaksrivats Thirumalai , Alexander G. Dean Extending STI for demanding hard-real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Ermedahl , Friedhelm Stappert , Jakob Engblom Clustered calculation of worst-case execution times. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Poplavko , Twan Basten , Marco Bekooij , Jef L. van Meerbergen , Bart Mesman Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Juanjo Noguera , Rosa M. Badia System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Lau , Stefan Schoenmackers , Timothy Sherwood , Brad Calder Reducing code size with echo instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Montserrat Ros , Peter Sutton Compiler optimization and ordering effects on VLIW code compression. [Citation Graph (0, 0)][DBLP ] Conf ] Partha Biswas , Nikil D. Dutt Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna V. Palem Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices. [Citation Graph (0, 0)][DBLP ] Conf ] Ann Gordon-Ross , Frank Vahid Frequent loop detection using efficient non-intrusive on-chip hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv A. Ravindran , Robert M. Senger , Eric D. Marsman , Ganesh S. Dasika , Matthew R. Guthaus , Scott A. Mahlke , Richard B. Brown Increasing the number of effective registers in a low-power processor using a windowed register file. [Citation Graph (0, 0)][DBLP ] Conf ] David Goodwin , Darin Petkov Automatic generation of application specific processors. [Citation Graph (0, 0)][DBLP ] Conf ] Osvaldo Colavin , Davide Rizzo A scalable wide-issue clustered VLIW with a reconfigurable interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Hillery C. Hunter , Jaime H. Moreno A new look at exploiting data parallelism in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Baleani , Alberto Ferrari , Leonardo Mangeruca , Alberto L. Sangiovanni-Vincentelli , Maurizio Peri , Saverio Pezzini Fault-tolerant platforms for automotive safety-critical applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chidamber Kulkarni , Matthias Gries , Christian Sauer , Kurt Keutzer Programming challenges in network processor deployment. [Citation Graph (0, 0)][DBLP ] Conf ] Ramnath Venugopalan , Prasanth Ganesan , Pushkin Peddabachagari , Alexander G. Dean , Frank Mueller , Mihail L. Sichitiu Encryption overhead in embedded systems and sensor network nodes: modeling and analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Dino Oliva , Rainer Buchty , Nevin Heintze AES and the cryptonite crypto processor. [Citation Graph (0, 0)][DBLP ] Conf ] Binu K. Mathew , Al Davis , Zhen Fang A low-power accelerator for the SPHINX 3 speech recognition system. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Krishna , Scott A. Mahlke , Todd M. Austin Architectural optimizations for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Zhong , Niraj K. Jha Graphical user interface energy characterization for handheld computers. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Mohanty , Viktor K. Prasanna A hierarchical approach for energy efficient application design using heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ankush Varma , Brinda Ganesh , Mainak Sen , Suchismita Roy Choudhury , Lakshmi Srinivasan , Bruce L. Jacob A control-theoretic approach to dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh C. Suresh , Banit Agrawal , Jun Yang , Walid A. Najjar , Laxmi N. Bhuyan Power efficient encoding techniques for off-chip data buses. [Citation Graph (0, 0)][DBLP ] Conf ] Sumesh Udayakumaran , Rajeev Barua Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Mahmut T. Kandemir , Hendra Saputra , Mary Jane Irwin Exploiting bank locality in multi-bank memories. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Darte , Robert Schreiber , Gilles Villard Lattice-based memory allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhang 0002 , Mahmut T. Kandemir , Anand Sivasubramaniam , Mary Jane Irwin Performance, energy, and reliability tradeoffs in replicating hot cache lines. [Citation Graph (0, 0)][DBLP ] Conf ] Federico Angiolini , Luca Benini , Alberto Caprara Polynomial-time algorithm for on-chip scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] 