Conferences in DBLP
Kees A. Vissers Programming models and architectures for FPGA platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Ali El-Haj-Mahmoud , Eric Rotenberg Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Ozcan Ozturk , Mustafa Karaköy Dynamic on-chip memory management for chip multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ken W. Batcher , Robert A. Walker Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. [Citation Graph (0, 0)][DBLP ] Conf ] Jayaprakash Pisharath , Alok N. Choudhary , Mahmut T. Kandemir Reducing energy consumption of queries in memory-resident database systems. [Citation Graph (0, 0)][DBLP ] Conf ] Binu K. Mathew , Al Davis , Michael Parker A low power architecture for embedded perception. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Sherwood , Mark Oskin , Brad Calder Balancing design options with Sherpa. [Citation Graph (0, 0)][DBLP ] Conf ] Pan Yu , Tulika Mitra Scalable custom instructions identification for instruction-set extensible processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jesus Garcia , Mark G. Arnold , Leonidas L. Bleris , Mayuresh V. Kothare LNS architectures for embedded model predictive control processors. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Beltrame , Gianluca Palermo , Donatella Sciuto , Cristina Silvano Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Musaravakkam S. Krishnan Disk drive energy optimization for audio-video applications. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Eisley , Li-Shiuan Peh High-level power analysis for on-chip networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoxiong Hua , Gang Qu Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee. [Citation Graph (0, 0)][DBLP ] Conf ] Bramha Allu , Wei Zhang 0002 Static next sub-bank prediction for drowsy instruction cache. [Citation Graph (0, 0)][DBLP ] Conf ] Montserrat Ros , Peter Sutton A hamming distance based VLIW/EPIC code compression technique. [Citation Graph (0, 0)][DBLP ] Conf ] Linwei Niu , Gang Quan Reducing both dynamic and leakage energy consumption for hard real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhang 0002 , Bramha Allu Loop-based leakage control for branch predictors. [Citation Graph (0, 0)][DBLP ] Conf ] John Cornish Balanced energy optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Ramakrishnan Venkitaraman , Gopal Gupta Static program analysis of embedded executable assembly code. [Citation Graph (0, 0)][DBLP ] Conf ] Vasanth Asokan , Alexander G. Dean Providing time- and space- efficient procedure calls for asynchronous software thread integration. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider , Jens Brandt , Tobias Schüle Causality analysis of synchronous programs with delayed actions. [Citation Graph (0, 0)][DBLP ] Conf ] Meilin Liu , Qingfeng Zhuge , Zili Shao , Edwin Hsing-Mean Sha General loop fusion technique for nested loops considering timing and code size. [Citation Graph (0, 0)][DBLP ] Conf ] David Berner , Jean-Pierre Talpin , Paul Le Guernic , Sandeep K. Shukla Modular design through component abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Valentina Salapura , Christos J. Georgiou , Indira Nair An efficient system-on-a-chip design methodology for networking applications. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandru Turjan , Bart Kienhuis , Ed F. Deprettere Translating affine nested-loop programs to process networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Kiemb , Kiyoung Choi Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Carr , Philip H. Sweany Automatic data partitioning for the agere payload plus network processor. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Verdoolaege , Rachid Seghir , Kristof Beyls , Vincent Loechner , Maurice Bruynooghe Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Federico Angiolini , Francesco Menichelli , Alberto Ferrero , Luca Benini , Mauro Olivieri A post-compiler approach to scratchpad mapping of code. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Guillon , Fabrice Rastello , Thierry Bidault , Florent Bouchez Procedure placement using temporal-ordering information: dealing with code size expansion. [Citation Graph (0, 0)][DBLP ] Conf ] Surupa Biswas , Matthew Simpson , Rajeev Barua Memory overflow protection for embedded systems using run-time checks, reuse and compression. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaotong Zhuang , Tao Zhang , Hsien-Hsin S. Lee , Santosh Pande Hardware assisted control flow obfuscation for embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Matsuoka , Patrick Schaumont , Kris Tiri , Ingrid Verbauwhede Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. [Citation Graph (0, 0)][DBLP ] Conf ] 