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Conferences in DBLP

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) (cases)
2000 (conf/cases/2000)

  1. Amir Pnueli
    Rigorous development of embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:1- [Conf]
  2. Daniel Weil, Valérie Bertin, Etienne Closse, Michel Poize, Patrick Venier, Jacques Pulou
    Efficient compilation of ESTEREL for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:2-8 [Conf]
  3. Fridtjof Siebert
    Eliminating external fragmentation in a non-moving garbage collector for Java. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:9-17 [Conf]
  4. Jeff Tsay, Christopher Hylands, Edward Lee
    A code generation framework for Java component-based designs. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:18-25 [Conf]
  5. Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert
    A joined architecture/compiler design environment for ASIPs. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:26-33 [Conf]
  6. Koen Danckaert, Francky Catthoor, Hugo De Man
    A preprocessing step for global loop transformations for data transfer optimization. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:34-40 [Conf]
  7. Michel Barreteau, Juliette Mattioli, Thierry Grandpierre, Christophe Lavarenne, Yves Sorel, Philippe Bonnot, Philippe Kajfasz
    PROMPT: a mapping environment for telecom applications on "system-on-a-chip". [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:41-47 [Conf]
  8. Antti Takko, Marko Hännikäinen, Jarno Knuutila, Timo Hämäläinen, Jukka Saarinen
    Embedding SDL implemented protocols into DSP. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:48-56 [Conf]
  9. Timothy J. Callahan, John Wawrzynek
    Adapting software pipelining for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:57-64 [Conf]
  10. Randall S. Janka, Linda M. Wills
    Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:65-70 [Conf]
  11. Santosh G. Abraham, B. Ramakrishna Rau
    Efficient design space exploration in PICO. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:71-79 [Conf]
  12. Prashant Arora, Rajesh K. Gupta
    Design and implementation of a hierarchical exception handling extension to systemC. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:80-84 [Conf]
  13. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:85-93 [Conf]
  14. Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin
    Code generator optimizations for the ST120 DSP-MCU core. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:93-102 [Conf]
  15. Peng Yang, Dirk Desmet, Francky Catthoor, Diederik Verkest
    Dynamic scheduling of concurrent tasks with cost performance trade-off. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:103-109 [Conf]
  16. Shige Wang, Kang G. Shin
    An architecture for embedded software integration using reusable components. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:110-118 [Conf]
  17. B. Ramakrishna Rau
    The era of embedded computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:119- [Conf]
  18. Hsien-Hsin S. Lee, Gary S. Tyson
    Region-based caching: an energy-delay efficient memory architecture for embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:120-127 [Conf]
  19. Tor M. Aamodt, Paul Chow
    Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:128-137 [Conf]
  20. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Energy-oriented compiler optimizations for partitioned memory architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:138-147 [Conf]
  21. Yonghong Song, Yuan Lin
    Unroll-and-jam for imperfectly-nested loops in DSP applications. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:148-156 [Conf]
  22. Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik
    Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:157-164 [Conf]
  23. Afzal Malik, Bill Moyer, Dan Cermak
    A programmable unified cache architecture for embedded applications. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:165-171 [Conf]
  24. Michael J. Schulte, Pablo I. Balzola, Jie Ruan, C. John Glossner
    Parallel saturating multioperand adders. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:172-179 [Conf]
  25. Mohamed Shalan, Vincent John Mooney III
    A dynamic memory management unit for embedded real-time system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:180-186 [Conf]
  26. Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky
    A first-step towards an architecture tuning methodology for low power. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:187-192 [Conf]
  27. Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
    Flexible instruction processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:193-200 [Conf]
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