Conferences in DBLP
Amir Pnueli Rigorous development of embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Weil , Valérie Bertin , Etienne Closse , Michel Poize , Patrick Venier , Jacques Pulou Efficient compilation of ESTEREL for real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Fridtjof Siebert Eliminating external fragmentation in a non-moving garbage collector for Java. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Tsay , Christopher Hylands , Edward Lee A code generation framework for Java component-based designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Teich , Ralph Weper , Dirk Fischer , Stefan Trinkert A joined architecture/compiler design environment for ASIPs. [Citation Graph (0, 0)][DBLP ] Conf ] Koen Danckaert , Francky Catthoor , Hugo De Man A preprocessing step for global loop transformations for data transfer optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Barreteau , Juliette Mattioli , Thierry Grandpierre , Christophe Lavarenne , Yves Sorel , Philippe Bonnot , Philippe Kajfasz PROMPT: a mapping environment for telecom applications on "system-on-a-chip". [Citation Graph (0, 0)][DBLP ] Conf ] Antti Takko , Marko Hännikäinen , Jarno Knuutila , Timo Hämäläinen , Jukka Saarinen Embedding SDL implemented protocols into DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Callahan , John Wawrzynek Adapting software pipelining for reconfigurable computing. [Citation Graph (0, 0)][DBLP ] Conf ] Randall S. Janka , Linda M. Wills Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh G. Abraham , B. Ramakrishna Rau Efficient design space exploration in PICO. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Arora , Rajesh K. Gupta Design and implementation of a hierarchical exception handling extension to systemC. [Citation Graph (0, 0)][DBLP ] Conf ] Malay Haldar , Anshuman Nayak , Alok N. Choudhary , Prithviraj Banerjee Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît Dupont de Dinechin , François de Ferrière , Christophe Guillon , Artour Stoutchinin Code generator optimizations for the ST120 DSP-MCU core. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Yang , Dirk Desmet , Francky Catthoor , Diederik Verkest Dynamic scheduling of concurrent tasks with cost performance trade-off. [Citation Graph (0, 0)][DBLP ] Conf ] Shige Wang , Kang G. Shin An architecture for embedded software integration using reusable components. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau The era of embedded computing. [Citation Graph (0, 0)][DBLP ] Conf ] Hsien-Hsin S. Lee , Gary S. Tyson Region-based caching: an energy-delay efficient memory architecture for embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tor M. Aamodt , Paul Chow Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Delaluz , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin Energy-oriented compiler optimizations for partitioned memory architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yonghong Song , Yuan Lin Unroll-and-jam for imperfectly-nested loops in DSP applications. [Citation Graph (0, 0)][DBLP ] Conf ] Subramanian Rajagopalan , Manish Vachharajani , Sharad Malik Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Afzal Malik , Bill Moyer , Dan Cermak A programmable unified cache architecture for embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Schulte , Pablo I. Balzola , Jie Ruan , C. John Glossner Parallel saturating multioperand adders. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Shalan , Vincent John Mooney III A dynamic memory management unit for embedded real-time system-on-a-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Frank Vahid , Tony Givargis , Roman L. Lysecky A first-step towards an architecture tuning methodology for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Shay Ping Seng , Wayne Luk , Peter Y. K. Cheung Flexible instruction processors. [Citation Graph (0, 0)][DBLP ] Conf ] 