Conferences in DBLP
Liang-Gee Chen Dances with multimedia: embedded video codec design. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Nakashima , Masahiro Konishi , Takashi Nakada An accurate and efficient simulation-based analysis for worst case interruption delay. [Citation Graph (0, 0)][DBLP ] Conf ] Won So , Alexander G. Dean Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP. [Citation Graph (0, 0)][DBLP ] Conf ] John Cavazos , Christophe Dubach , Felix V. Agakov , Edwin V. Bonilla , Michael F. P. O'Boyle , Grigori Fursin , Olivier Temam Automatic performance model construction for the fast software exploration of new hardware designs. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Heon Jung , Sung-Hwan Bae , Jaemok Lee , Soo-Mook Moon , Jong Kuk Park Supporting precise garbage collection in Java Bytecode-to-C ahead-of-time compiler for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Hines , David B. Whalley , Gary S. Tyson Adapting compilation techniques to enhance the packing of instructions into registers. [Citation Graph (0, 0)][DBLP ] Conf ] Ankush Varma , Muhammad Yaqub Afridi , Akin Akturk , Paul Klein , Allen R. Hefner , Bruce L. Jacob Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Peter Löb , Rainer Buchty , Wolfgang Karl A network agent for diagnosis and analysis of real-time Ethernet networks. [Citation Graph (0, 0)][DBLP ] Conf ] Rachid Seghir , Vincent Loechner Memory optimization by counting points in integer transformations of parametric polytopes. [Citation Graph (0, 0)][DBLP ] Conf ] Ka-Ming Keung , Akhilesh Tyagi State space reconfigurability: an implementation architecture for self modifying finite automata. [Citation Graph (0, 0)][DBLP ] Conf ] Arran Derbyshire , Tobias Becker , Wayne Luk Incremental elaboration for run-time reconfigurable hardware designs. [Citation Graph (0, 0)][DBLP ] Conf ] Taeho Kgil , Trevor N. Mudge FlashCache: a NAND flash memory file cache for low power web servers. [Citation Graph (0, 0)][DBLP ] Conf ] Mats Brorsson , Mikael Collin Adaptive and flexible dictionary code compression for embedded applications. [Citation Graph (0, 0)][DBLP ] Conf ] Lan S. Bai , Lei Yang , Robert P. Dick Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunchul Park , Kevin Fan , Manjunath Kudlur , Scott A. Mahlke Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Nathan Clark , Amir Hormati , Scott A. Mahlke , Sami Yehia Scalable subgraph mapping for acyclic computation accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] J. George , B. Marr , Bilge E. S. Akgul , Krishna V. Palem Probabilistic arithmetic and energy efficient embedded signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Chengmo Yang , Alex Orailoglu Power efficient branch prediction through early identification of branch addresses. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Hyuk Woo , Mrinmoy Ghosh , Emre Özer , Stuart Biles , Hsien-Hsin S. Lee Reducing energy of virtual cache synonym lookup using bloom filters. [Citation Graph (0, 0)][DBLP ] Conf ] Lukasz Strozek , David Brooks Efficient architectures through application clustering and architectural heterogeneity. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Scholz , Bernd Burgstaller , Jingling Xue Minimizing bank selection instructions for partitioned memory architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yoonseo Choi , Hwansoo Han Protected heap sharing for memory-constrained java environments. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Egger , Chihun Kim , Choonki Jang , Yoonsung Nam , Jaejin Lee , Sang Lyul Min A dynamic code placement technique for scratchpad memory using postpass optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Seon-Yeong Park , Dawoon Jung , Jeong-Uk Kang , Jinsoo Kim , Joonwon Lee CFLRU: a replacement algorithm for flash memory. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bonzini , Laura Pozzi Code transformation strategies for extensible embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Neil C. Audsley , Michael Ward Syntax-driven implementation of software programming language control constructs and expressions on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kim M. Hazelwood , Artur Klauser A dynamic binary instrumentation engine for the ARM architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Carro , José F. Morales , Henk L. Muller , Germán Puebla , Manuel V. Hermenegildo High-level languages for small devices: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] John Gilbert , David M. Abrahamson Adaptive object code compression. [Citation Graph (0, 0)][DBLP ] Conf ] Asadollah Shahbahrami , Ben H. H. Juurlink , Stamatis Vassiliadis Limitations of special-purpose instructions for similarity measurements in media SIMD extensions. [Citation Graph (0, 0)][DBLP ] Conf ] Chinnakrishnan Ballapuram , Kiran Puttaswamy , Gabriel H. Loh , Hsien-Hsin S. Lee Entropy-based low power data TLB design. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Hardnett , Krishna V. Palem , Yogesh Chobe Compiler optimization of embedded applications for an adaptive SoC architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Hoover , Forrest Brewer , Timothy Sherwood Extensible control architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Duo Liu , Bei Hua , Xianghui Hu , Xinan Tang High-performance packet classification algorithm for many-core and multithreaded network processor. [Citation Graph (0, 0)][DBLP ] Conf ] Anahita Shayesteh , Glenn Reinman , Norman P. Jouppi , Timothy Sherwood , Suleyman Sair Improving the performance and power efficiency of shared helpers in CMPs. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Hoover , Forrest Brewer , Timothy Sherwood A case study of multi-threading in the embedded space. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Hempstead , Gu-Yeon Wei , David Brooks Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations. [Citation Graph (0, 0)][DBLP ] Conf ] Razvan Racu , Arne Hamann , Rolf Ernst , Bren Mochocki , Xiaobo Sharon Hu Methods for power optimization in distributed embedded systems with real-time requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Eisley , Vassos Soteriou , Li-Shiuan Peh High-level power analysis for multi-core chips. [Citation Graph (0, 0)][DBLP ] Conf ] Vivy Suhendra , Chandrashekar Raghavan , Tulika Mitra Integrated scratchpad memory optimization and task scheduling for MPSoC architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kyoungwoo Lee , Aviral Shrivastava , Ilya Issenin , Nikil Dutt , Nalini Venkatasubramanian Mitigating soft error failures for multimedia applications by selective data protection. [Citation Graph (0, 0)][DBLP ] Conf ] Jason A. Blome , Shantanu Gupta , Shuguang Feng , Scott A. Mahlke Cost-efficient soft error protection for embedded microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] 