Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2008 (conf/isca/2008)

1. 
   Achieving Out-of-Order Performance with Almost In-Order Complexity. [Citation Graph (, )][DBLP]
   
   
2. 
   Fetch-Criticality Reduction through Control Independence. [Citation Graph (, )][DBLP]
   
   
3. 
   A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP]
   
   
4. 
   Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. [Citation Graph (, )][DBLP]
   
   
5. 
   A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. [Citation Graph (, )][DBLP]
   
   
6. 
   Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. [Citation Graph (, )][DBLP]
   
   
7. 
   Technology-Driven, Highly-Scalable Dragonfly Topology. [Citation Graph (, )][DBLP]
   
   
8. 
   Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. [Citation Graph (, )][DBLP]
   
   
9. 
   Polymorphic On-Chip Networks. [Citation Graph (, )][DBLP]
   
   
10. 
    Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory. [Citation Graph (, )][DBLP]
    
    
11. 
    TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. [Citation Graph (, )][DBLP]
    
    
12. 
    Flexible Decoupled Transactional Memory Support. [Citation Graph (, )][DBLP]
    
    
13. 
    Corona: System Implications of Emerging Nanophotonic Technology. [Citation Graph (, )][DBLP]
    
    
14. 
    Microcoded Architectures for Ion-Tap Quantum Computers. [Citation Graph (, )][DBLP]
    
    
15. 
    Running a Quantum Circuit at the Speed of Data. [Citation Graph (, )][DBLP]
    
    
16. 
    ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. [Citation Graph (, )][DBLP]
    
    
17. 
    Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. [Citation Graph (, )][DBLP]
    
    
18. 
    Counting Dependence Predictors. [Citation Graph (, )][DBLP]
    
    
19. 
    Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. [Citation Graph (, )][DBLP]
    
    
20. 
    iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. [Citation Graph (, )][DBLP]
    
    
21. 
    MIRA: A Multi-layered On-Chip Interconnect Router Architecture. [Citation Graph (, )][DBLP]
    
    
22. 
    Rerun: Exploiting Episodes for Lightweight Memory Race Recording. [Citation Graph (, )][DBLP]
    
    
23. 
    Atom-Aid: Detecting and Surviving Atomicity Violations. [Citation Graph (, )][DBLP]
    
    
24. 
    DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. [Citation Graph (, )][DBLP]
    
    
25. 
    Intra-disk Parallelism: An Idea Whose Time Has Come. [Citation Graph (, )][DBLP]
    
    
26. 
    Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments. [Citation Graph (, )][DBLP]
    
    
27. 
    Improving NAND Flash Based Disk Caches. [Citation Graph (, )][DBLP]
    
    
28. 
    Online Estimation of Architectural Vulnerability Factor for Soft Errors. [Citation Graph (, )][DBLP]
    
    
29. 
    A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. [Citation Graph (, )][DBLP]
    
    
30. 
    Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
31. 
    Flexible Hardware Acceleration for Instruction-Grain Program Monitoring. [Citation Graph (, )][DBLP]
    
    
32. 
    VEAL: Virtualized Execution Accelerator for Loops. [Citation Graph (, )][DBLP]
    
    
33. 
    From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware. [Citation Graph (, )][DBLP]
    
    
34. 
    Software-Controlled Priority Characterization of POWER5 Processor. [Citation Graph (, )][DBLP]
    
    
35. 
    Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction. [Citation Graph (, )][DBLP]
    
    
36. 
    Atomic Vector Operations on Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
37. 
    3D-Stacked Memory Architectures for Multi-core Processors. [Citation Graph (, )][DBLP]