|
Conferences in DBLP
Moving the needle, computer architecture research in academe and industry. [Citation Graph (, )][DBLP]
WiDGET: Wisconsin decoupled grid execution tiles. [Citation Graph (, )][DBLP]
Forwardflow: a scalable core for power-constrained CMPs. [Citation Graph (, )][DBLP]
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. [Citation Graph (, )][DBLP]
Understanding sources of inefficiency in general-purpose chips. [Citation Graph (, )][DBLP]
Translation caching: skip, don't walk (the page table). [Citation Graph (, )][DBLP]
High performance cache replacement using re-reference interval prediction (RRIP). [Citation Graph (, )][DBLP]
The virtual write queue: coordinating DRAM and last-level cache policies. [Citation Graph (, )][DBLP]
Reducing cache power with low-cost, multi-bit error-correcting codes. [Citation Graph (, )][DBLP]
An intra-chip free-space optical interconnect. [Citation Graph (, )][DBLP]
Aérgia: exploiting packet latency slack in on-chip networks. [Citation Graph (, )][DBLP]
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. [Citation Graph (, )][DBLP]
Re-architecting DRAM memory systems with monolithically integrated silicon photonics. [Citation Graph (, )][DBLP]
Use ECP, not ECC, for hard failures in resistive memories. [Citation Graph (, )][DBLP]
Morphable memory system: a robust architecture for exploiting multi-level phase change memories. [Citation Graph (, )][DBLP]
SieveStore: a highly-selective, ensemble-level disk cache for cost-performance. [Citation Graph (, )][DBLP]
Rethinking DRAM design and organization for energy-constrained multi-cores. [Citation Graph (, )][DBLP]
LReplay: a pending period based deterministic replay scheme. [Citation Graph (, )][DBLP]
Timetraveler: exploiting acyclic races for optimizing memory race recording. [Citation Graph (, )][DBLP]
Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races. [Citation Graph (, )][DBLP]
ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations. [Citation Graph (, )][DBLP]
Shared caches in multicores: the good, the bad, and the ugly. [Citation Graph (, )][DBLP]
Dynamic warp subdivision for integrated branch and memory divergence tolerance. [Citation Graph (, )][DBLP]
A dynamically configurable coprocessor for convolutional neural networks. [Citation Graph (, )][DBLP]
RETCON: transactional repair without replay. [Citation Graph (, )][DBLP]
Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications. [Citation Graph (, )][DBLP]
An integrated GPU power and performance model. [Citation Graph (, )][DBLP]
A case for FAME: FPGA architecture model execution. [Citation Graph (, )][DBLP]
Evolution of thread-level parallelism in desktop applications. [Citation Graph (, )][DBLP]
Web search using mobile cores: quantifying and mitigating the price of efficiency. [Citation Graph (, )][DBLP]
The impact of management operations on the virtualized datacenter. [Citation Graph (, )][DBLP]
Energy proportional datacenter networks. [Citation Graph (, )][DBLP]
Improving the future by examining the past. [Citation Graph (, )][DBLP]
The rebirth of neural networks. [Citation Graph (, )][DBLP]
NoHype: virtualized cloud infrastructure without the virtualization. [Citation Graph (, )][DBLP]
Modeling critical sections in Amdahl's law and its implications for multicore design. [Citation Graph (, )][DBLP]
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. [Citation Graph (, )][DBLP]
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. [Citation Graph (, )][DBLP]
IVEC: off-chip memory integrity protection for both security and reliability. [Citation Graph (, )][DBLP]
Sentry: light-weight auxiliary memory access control. [Citation Graph (, )][DBLP]
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. [Citation Graph (, )][DBLP]
Cohesion: a hybrid memory model for accelerators. [Citation Graph (, )][DBLP]
Data marshaling for multi-core architectures. [Citation Graph (, )][DBLP]
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. [Citation Graph (, )][DBLP]
Using hardware vulnerability factors to enhance AVF analysis. [Citation Graph (, )][DBLP]
Necromancer: enhancing system throughput by animating dead cores. [Citation Graph (, )][DBLP]
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. [Citation Graph (, )][DBLP]
Relax: an architectural framework for software recovery of hardware faults. [Citation Graph (, )][DBLP]
|