Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2010 (conf/isca/2010)

1. 
   Moving the needle, computer architecture research in academe and industry. [Citation Graph (, )][DBLP]
   
   
2. 
   WiDGET: Wisconsin decoupled grid execution tiles. [Citation Graph (, )][DBLP]
   
   
3. 
   Forwardflow: a scalable core for power-constrained CMPs. [Citation Graph (, )][DBLP]
   
   
4. 
   Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. [Citation Graph (, )][DBLP]
   
   
5. 
   Understanding sources of inefficiency in general-purpose chips. [Citation Graph (, )][DBLP]
   
   
6. 
   Translation caching: skip, don't walk (the page table). [Citation Graph (, )][DBLP]
   
   
7. 
   High performance cache replacement using re-reference interval prediction (RRIP). [Citation Graph (, )][DBLP]
   
   
8. 
   The virtual write queue: coordinating DRAM and last-level cache policies. [Citation Graph (, )][DBLP]
   
   
9. 
   Reducing cache power with low-cost, multi-bit error-correcting codes. [Citation Graph (, )][DBLP]
   
   
10. 
    An intra-chip free-space optical interconnect. [Citation Graph (, )][DBLP]
    
    
11. 
    Aérgia: exploiting packet latency slack in on-chip networks. [Citation Graph (, )][DBLP]
    
    
12. 
    Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. [Citation Graph (, )][DBLP]
    
    
13. 
    Re-architecting DRAM memory systems with monolithically integrated silicon photonics. [Citation Graph (, )][DBLP]
    
    
14. 
    Use ECP, not ECC, for hard failures in resistive memories. [Citation Graph (, )][DBLP]
    
    
15. 
    Morphable memory system: a robust architecture for exploiting multi-level phase change memories. [Citation Graph (, )][DBLP]
    
    
16. 
    SieveStore: a highly-selective, ensemble-level disk cache for cost-performance. [Citation Graph (, )][DBLP]
    
    
17. 
    Rethinking DRAM design and organization for energy-constrained multi-cores. [Citation Graph (, )][DBLP]
    
    
18. 
    LReplay: a pending period based deterministic replay scheme. [Citation Graph (, )][DBLP]
    
    
19. 
    Timetraveler: exploiting acyclic races for optimizing memory race recording. [Citation Graph (, )][DBLP]
    
    
20. 
    Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races. [Citation Graph (, )][DBLP]
    
    
21. 
    ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations. [Citation Graph (, )][DBLP]
    
    
22. 
    Shared caches in multicores: the good, the bad, and the ugly. [Citation Graph (, )][DBLP]
    
    
23. 
    Dynamic warp subdivision for integrated branch and memory divergence tolerance. [Citation Graph (, )][DBLP]
    
    
24. 
    A dynamically configurable coprocessor for convolutional neural networks. [Citation Graph (, )][DBLP]
    
    
25. 
    RETCON: transactional repair without replay. [Citation Graph (, )][DBLP]
    
    
26. 
    Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications. [Citation Graph (, )][DBLP]
    
    
27. 
    An integrated GPU power and performance model. [Citation Graph (, )][DBLP]
    
    
28. 
    A case for FAME: FPGA architecture model execution. [Citation Graph (, )][DBLP]
    
    
29. 
    Evolution of thread-level parallelism in desktop applications. [Citation Graph (, )][DBLP]
    
    
30. 
    Web search using mobile cores: quantifying and mitigating the price of efficiency. [Citation Graph (, )][DBLP]
    
    
31. 
    The impact of management operations on the virtualized datacenter. [Citation Graph (, )][DBLP]
    
    
32. 
    Energy proportional datacenter networks. [Citation Graph (, )][DBLP]
    
    
33. 
    Improving the future by examining the past. [Citation Graph (, )][DBLP]
    
    
34. 
    The rebirth of neural networks. [Citation Graph (, )][DBLP]
    
    
35. 
    NoHype: virtualized cloud infrastructure without the virtualization. [Citation Graph (, )][DBLP]
    
    
36. 
    Modeling critical sections in Amdahl's law and its implications for multicore design. [Citation Graph (, )][DBLP]
    
    
37. 
    Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. [Citation Graph (, )][DBLP]
    
    
38. 
    Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. [Citation Graph (, )][DBLP]
    
    
39. 
    IVEC: off-chip memory integrity protection for both security and reliability. [Citation Graph (, )][DBLP]
    
    
40. 
    Sentry: light-weight auxiliary memory access control. [Citation Graph (, )][DBLP]
    
    
41. 
    Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
42. 
    Cohesion: a hybrid memory model for accelerators. [Citation Graph (, )][DBLP]
    
    
43. 
    Data marshaling for multi-core architectures. [Citation Graph (, )][DBLP]
    
    
44. 
    Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. [Citation Graph (, )][DBLP]
    
    
45. 
    Using hardware vulnerability factors to enhance AVF analysis. [Citation Graph (, )][DBLP]
    
    
46. 
    Necromancer: enhancing system throughput by animating dead cores. [Citation Graph (, )][DBLP]
    
    
47. 
    Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. [Citation Graph (, )][DBLP]
    
    
48. 
    Relax: an architectural framework for software recovery of hardware faults. [Citation Graph (, )][DBLP]