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Conferences in DBLP

IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2005 (conf/iscas/2005)

  1. Aditya Bansal, Kaushik Roy
    Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:1-4 [Conf]
  2. Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
    Limits to performance spread tuning using adaptive voltage and body biasing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:5-8 [Conf]
  3. James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De
    Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:9-12 [Conf]
  4. Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba
    Device technology for body biasing scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:13-16 [Conf]
  5. Masayuki Miyazaki, Goichi Ono, Takayuki Kawahara
    Optimum threshold-voltage tuning for low-power, high-performance microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:17-20 [Conf]
  6. Ruchir Puri, David S. Kung, Leon Stok
    Minimizing power with flexible voltage islands. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:21-24 [Conf]
  7. Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga
    Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:25-28 [Conf]
  8. Mahmoud Elassal, Ashok Kumar, Magdy Bayoumi
    A systematic framework for high throughput MAP decoder VLSI architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:29-32 [Conf]
  9. Saman S. Abeysekera, Charoensak Charayaphan
    System on chip FPGA design of an FM demodulator using a Kalman band-pass sigma-delta architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:33-36 [Conf]
  10. Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
    High level hardware/software communication estimation in shared memory architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:37-40 [Conf]
  11. Yutian Zhao, Ahmet T. Erdogan, Tughrul Arslan
    A novel low-power reconfigurable FFT processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:41-44 [Conf]
  12. Bradley R. Quinton, Steven J. E. Wilton
    Concentrator access networks for programmable logic cores on SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:45-48 [Conf]
  13. Maria-Gabriella Di Benedetto, Guerino Giancola
    A collision-based model for multi user interference in impulse radio UWB networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:49-52 [Conf]
  14. Luca Reggiani, Gian Mario Maggio
    On the acquisition time for serial and parallel code search in UWB impulse radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:53-56 [Conf]
  15. Chun Yi Lee, Christofer Toumazou
    Ultra-low power UWB for real time biomedical wireless sensing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:57-60 [Conf]
  16. Won Namgoong, Lei Feng
    Digitizing of UWB signals based on frequency channelization. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:61-64 [Conf]
  17. Sang-Min Kim, Jun Tang, Keshab K. Parhi
    Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:65-68 [Conf]
  18. Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy
    A novel covalent redundant binary Booth encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:69-72 [Conf]
  19. Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
    A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:73-76 [Conf]
  20. Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang
    A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:77-80 [Conf]
  21. Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo
    A framework for the design of error-aware power-efficient fixed-width Booth multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:81-84 [Conf]
  22. Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar
    A novel multiplexer based truncated array multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:85-88 [Conf]
  23. James E. Stine, Michael J. Schulte
    A combined two's complement and floating-point comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:89-92 [Conf]
  24. Yici Cai, Yibo Wang, Xianlong Hong
    A global interconnect optimization algorithm under accurate delay model using solution space smoothing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:93-96 [Conf]
  25. Yiqian Zhang, Xianlong Hong, Yici Cai
    An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:97-100 [Conf]
  26. Xinjie Wei, Yici Cai, Xianlong Hong
    Zero skew clock routing with tree topology construction using simulated annealing method. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:101-104 [Conf]
  27. Hao Yu, Lei He
    A sparsified vector potential equivalent circuit model for massively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:105-108 [Conf]
  28. Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn
    An efficient algorithm for simultaneous wire permutation, inversion, and spacing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:109-112 [Conf]
  29. Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
    Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:113-116 [Conf]
  30. Alberto Saiz-Vela, Pedro Luis Miribel-Català, Manuel Puig-Vidal, Josep Samitier
    An electron mobility independent pulse skipping regulator for a programmable CMOS charge pump. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:117-120 [Conf]
  31. Chiara Boffino, Alessandro Cabrini, Osama Khouri, Guido Torelli
    High-efficiency control structure for CMOS flash memory charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:121-124 [Conf]
  32. Mark Hooper, Matt Kucic, Paul E. Hasler
    Integration of high voltage charge-pumps in a submicron standard CMOS process for programming analog floating-gate circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:125-128 [Conf]
  33. Heng-Ming Hsu, Tai-Hsing Lee
    Optimum quiescent point of integrated power CMOS transistor for wireless portable applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:129-132 [Conf]
  34. Mohammad R. Hoque, T. Ahmad, Todd McNutt, H. Alan Mantooth, Mohommad M. Mojarradi
    Design technique of an on-chip, high-voltage charge pump in SOI. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:133-136 [Conf]
  35. Eugenio Culurciello, Philippe O. Pouliquen, Andreas G. Andreou, Kim Strohbehn, Steven E. Jaskulek
    A monolithic isolation amplifier in silicon-on-insulator CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:137-140 [Conf]
  36. Raimon Casanova, Junajo Lacort, Ángel Dieguez, Anna Arbat, Manel Puig, Josep Samitier, Marc Nierlich, Oliver Steinmetz, Oliver Scholz
    A specific integrated controller for nanomicroscopy and cellular manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:141-144 [Conf]
  37. Chris Clarke, John Taylor, Robert Rieger, Nick Donaldson
    A distributed neural signal sensor system. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:145-148 [Conf]
  38. Jierong Cheng, Say Wei Foo, Shankar M. Krishnan
    Automatic detection of region of interest and center point of left ventricle using watershed segmentation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:149-151 [Conf]
  39. Chin-Teng Lin, Yu-Chieh Chen, Ruei-Cheng Wu, Sheng-Fu Liang, Teng-Yi Huang
    Assessment of driver's driving performance and alertness using EEG-based fuzzy neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:152-155 [Conf]
  40. Sheng-Fu Liang, Chin-Teng Lin, Ruei-Cheng Wu, Teng-Yi Huang, Wen-Hung Chao
    Classification of driver's cognitive responses from EEG analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:156-159 [Conf]
  41. Takehiro Ito, Xiao Zhou, Takao Nishizeki
    Partitioning graphs of supply and demand. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:160-163 [Conf]
  42. Krishnaiyan Thulasiraman, Ying Xiao, Guoliang Xue
    Advances in QoS path(s) selection problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:164-167 [Conf]
  43. Tomiyuki Fukunaga, Qi-Wei Ge, Mitsuru Nakata
    On generating elementary T-invariants of Petri nets by linear programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:168-171 [Conf]
  44. Daisuke Takafuji, Toshimasa Watanabe
    Hierarchical extraction of a spanning planar subgraph maintaining clockwise directedness of cycles. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:172-175 [Conf]
  45. Hiroshi Tamura, Futoshi Tasaki, Masakazu Sengoku, Shoji Shinoda
    Scheduling problems for a class of parallel distributed systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:176-179 [Conf]
  46. Satoshi Tayu, Patrik Hurtig, Yoshiyasu Horikawa, Shuichi Ueno
    On the three-dimensional channel routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:180-183 [Conf]
  47. Brian P. Ginsburg, Anantha P. Chandrakasan
    An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:184-187 [Conf]
  48. Harri Lampinen, Pauli Perälä, Olli Vainio
    Novel successive-approximation algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:188-191 [Conf]
  49. Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata
    A 1V supply successive approximation ADC with rail-to-rail input voltage range. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:192-195 [Conf]
  50. D. Marche, Yves Gagnon, Yvon Savaria
    . A new switch compensation technique for inverted R-2R ladder DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:196-199 [Conf]
  51. Hamid Movahedian, Mehrdad Sharif Bakhtiar
    A new offset cancellation technique for folding ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:200-203 [Conf]
  52. Tomás Lahoz, Enrique Barajas, José Luis González
    Characterization and noise analysis of a 12-bit current steering digital-to-analog converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:204-207 [Conf]
  53. Belén Calvo, Maria Teresa Sanz, Santiago Celma
    High linear digitally programmable gain amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:208-211 [Conf]
  54. Chih-Yun Liu, Yi-Jan Emery Chen, Deuk Hyoun Heo
    Impact of bias schemes on Doherty power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:212-215 [Conf]
  55. Mikko Loikkanen, Juha Kostamovaara
    High current CMOS operational amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:216-219 [Conf]
  56. Yasutaka Haga, Hashem Zare-Hoseini, Laurence Berkovi, Izzet Kale
    Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:220-223 [Conf]
  57. Tong Ge, Meng Tong Tan, Joseph Sylvester Chang
    Design and analysis of a micropower low-voltage bang-bang control class D amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:224-227 [Conf]
  58. Christian Falconi, Giuliano Guarino, Arnaldo D'Amico
    Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [voltage regulator example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:228-231 [Conf]
  59. Jeffrey Harrison
    Formal synthesis of circuits using linear matrix inequalities. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:232-235 [Conf]
  60. Antônio Carlos M. de Queiroz
    Multiple resonance networks with incomplete energy transfer and operating with zero-state response. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:236-239 [Conf]
  61. Kai-Sheng Lu, Xiao-Yu Feng, Guo-Zhang Gao
    The separability, reducibility and controllability of RLCM networks over F(z). [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:240-243 [Conf]
  62. David G. Haigh, Paul M. Radmore
    Symbolic passive-RC circuit synthesis by admittance matrix expansion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:244-247 [Conf]
  63. David G. Haigh
    Symbolic active-RC circuit synthesis by admittance matrix expansion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:248-251 [Conf]
  64. Rogelio Palomera-Garcia
    Generation of equivalent circuits by FTFN relocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:252-255 [Conf]
  65. Mitsuji Muneyasu, Osamu Hisayasu, Kensaku Fujii, Takao Hinamoto
    An active noise control system based on simultaneous equations method without auxiliary filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:256-259 [Conf]
  66. Yegui Xiao, Liying Ma, Khashayar Khorasani, Akira Ikuta, Li Xu
    A filtered-X RLS based narrowband active noise control system in the presence of frequency mismatch. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:260-263 [Conf]
  67. Muhammad Tahir Akhtar, Masahide Abe, Masayuki Kawamata
    A method for online secondary path modeling in active noise control systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:264-267 [Conf]
  68. Say Wei Foo, T. N. Senthilkumar, C. Averty
    Active noise cancellation headset. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:268-271 [Conf]
  69. Naoto Sasaoka, Keisuke Sumi, Yoshio Itoh, Kensaku Fujii
    A new noise reduction system based on ALE and noise reconstruction filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:272-275 [Conf]
  70. Woon S. Gan, Sen M. Kuo, Jin Wei Feng
    Adaptive noise equalizer with equal-loudness compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:276-279 [Conf]
  71. Xiang Li, Hildegard Meyer-Ortmanns, Xiaofan Wang
    Chaotic and periodic spreading dynamics in discrete small-world networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:280-283 [Conf]
  72. Zhengping Fan, Guanrong Chen
    Pinning control of scale-free complex networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:284-287 [Conf]
  73. Chunguang Li, Jin-Qing Fang
    On-off intermittency in small-world networks of chaotic maps. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:288-291 [Conf]
  74. Chai Wah Wu
    Agreement and consensus problems in groups of autonomous agents with linear dynamics. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:292-295 [Conf]
  75. Maide Bucolo, Francesca Conti, Luigi Fortuna, Mattia Frasca
    3D dynamical networks to emulate complex neural phenomena. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:296-299 [Conf]
  76. Jinhu Lu, Henry Leung
    Synchronization: a fundamental phenomenon in complex dynamical networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:300-303 [Conf]
  77. Debing Liu, Yuwen He, Shipeng Li, Qingming Huang, Wen Gao
    Linear transform based motion compensated prediction for luminance intensity changes. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:304-307 [Conf]
  78. Changsung Kim, C. C. Jay Kuo
    A feature-based approach to fast H.264 intra/inter mode decision. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:308-311 [Conf]
  79. Hongtao Yu, Zhiping Lin, Feng Pan
    An improved rate control algorithm for H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:312-315 [Conf]
  80. Ci-Xun Zhang, Jian Lou, Lu Yu, Jie Dong, Wai-Kuen Cham
    The technique of pre-scaled integer transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:316-319 [Conf]
  81. Panos Nasiopoulos, L. Coria-Mendozal, Hassan Mansour, Adarsh Golikeri
    An improved error concealment algorithm for intra-frames in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:320-323 [Conf]
  82. Thomas Wedi, Stefan Wittmann
    Quantization offsets for video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:324-327 [Conf]
  83. Meng-Guang Tsai, Kuen-Suey Hou, Hen-Wai Tsao
    Iterative tri-stage decoding for turbo codes in partial response channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:328-331 [Conf]
  84. Matthieu Arzel, Cyril Lahuec, Fabrice Seguin, David Gnaedig, Michel Jézéquel
    . Analog slice turbo decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:332-335 [Conf]
  85. Stephen Bates, Gary Block
    A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:336-339 [Conf]
  86. Qingsheng Hu, Zhigong Wang, Jun Zhang, Jie Xiao
    Low complexity parallel Chien search architecture for RS decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:340-343 [Conf]
  87. Matthias Kamuf, John B. Anderson, Viktor Öwall
    Area and power efficient trellis computational blocks in 0.13µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:344-347 [Conf]
  88. Rajendra Katti, Xiaoyu Ruan
    S-code: new distance-3 MDS array codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:348-351 [Conf]
  89. A. Prasad Vinod, Edmund Ming-Kit Lai
    Design of low complexity high-speed pulse-shaping IIR filters for mobile communication receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:352-355 [Conf]
  90. Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng
    Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:356-359 [Conf]
  91. Yumi Takizawa, Cindy Bernadeth Tjitrosoewarno, Atsushi Fukasawa
    Multi-user receiver using conjugate gradient method for wideband CDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:360-363 [Conf]
  92. Lucian-Vasile Stoica, Sakari Tiuraniemi, Heikki Repo, Ian Oppermann
    An ultra wideband low complexity circuit transceiver architecture for sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:364-367 [Conf]
  93. Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao
    A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:368-371 [Conf]
  94. E. Shoukry, M. Mony, D. V. Plant
    Design of a fully integrated array of high-voltage digital-to-analog converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:372-375 [Conf]
  95. Lin Jia, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do
    A novel methodology for the design of LC tank VCO with low phase noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:376-379 [Conf]
  96. Yuan Yao, Yin Shi, Foster F. Dai
    A novel low-power input-independent MOS AC/DC charge pump. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:380-383 [Conf]
  97. Zhiqiang Gao, Jianguo Ma, Yizheng Ye, Mingyan Yu
    Large tuning band range of high frequency filter for wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:384-387 [Conf]
  98. Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D'Amico, Andrea Baschirotto
    Behavioral analysis and dimensioning of UMTS transmitters baseband blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:388-391 [Conf]
  99. Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
    A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:392-395 [Conf]
  100. Jiangnan Yan, Yuanjin Zheng, Yong Ping Xu
    A novel DC-offset cancelling circuit for DCR. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:396-399 [Conf]
  101. Chiara Ghidini, J. G. Aranda, Danilo Gerna, K. Kelliher, Christoph Baumhof
    A digitally programmable on-chip RC-oscillator in 0.25µm CMOS logic process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:400-403 [Conf]
  102. Si-Weng Fok, P. Cheong, Kam-Weng Tam, Rui Paulo Martins
    A novel microstrip bandpass filter design using asymmetric parallel coupled-line. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:404-407 [Conf]
  103. Yongru Gu, Keshab K. Parhi
    Pipelining Tomlinson-Harashima precoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:408-411 [Conf]
  104. Sebastián López, F. Tobajas, A. Villar, V. de Armas, José Francisco López, Roberto Sarmiento
    Low cost efficient architecture for H.264 motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:412-415 [Conf]
  105. Javier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner
    Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:416-419 [Conf]
  106. Wai-Chi Fang, C. Le, S. Taft
    On-board fault-tolerant SAR processor for spaceborne imaging radar systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:420-423 [Conf]
  107. Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi
    Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:424-427 [Conf]
  108. Rodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin
    Design space exploration on heterogeneous network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:428-431 [Conf]
  109. Yeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung
    A simple and cost effective video encoder with memory-reducing CAVLC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:432-435 [Conf]
  110. Xuequn Li, Haleh Vahedi, Radu Muresan, Stefano Gregori
    An integrated current flattening module for embedded cryptosystems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:436-439 [Conf]
  111. Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
    A pseudo-differential CMOS receiver insensitive to input common mode level. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:440-443 [Conf]
  112. Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
    Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:444-447 [Conf]
  113. Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
    High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:448-451 [Conf]
  114. Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
    A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:452-455 [Conf]
  115. Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen
    Case study of interconnect analysis for standing wave oscillator design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:456-459 [Conf]
  116. Johan Lambie, Francesc Moll Echeto, José Luis González, Antonio Rubio
    Asynchronous pulse logic cell for threshold logic and Boolean networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:460-463 [Conf]
  117. Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra
    Cascode buffer for monolithic voltage conversion operating at high input supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:464-467 [Conf]
  118. David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler
    Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:468-471 [Conf]
  119. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis
    A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:472-475 [Conf]
  120. Bogdan J. Falkowski, Cheng Fu
    Quaternary arithmetic helix transforms based on Kronecker product. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:476-479 [Conf]
  121. Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja
    Generalized fastest linearly independent arithmetic transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:480-483 [Conf]
  122. Bogdan J. Falkowski, Shixing Yan
    Fixed sign Walsh transform and its iterative hardware architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:484-487 [Conf]
  123. Bogdan J. Falkowski, Cheng Fu
    Generation of linearly independent transforms over GF(4). [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:488-491 [Conf]
  124. Xiaolang Yan, Ying Qin, Ye Yang, Haitong Ge
    A high performance architecture of EBCOT encoder in JPEG 2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:492-495 [Conf]
  125. A. Prasad Vinod, Edmund Ming-Kit Lai
    Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:496-499 [Conf]
  126. Tian-Bo Deng
    Complex-coefficient variable filter design using successive vector-array-decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:500-503 [Conf]
  127. Tian-Bo Deng
    Non-iterative WLS design of allpass variable fractional-delay digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:504-507 [Conf]
  128. Masayoshi Nakamoto, Yuji Maejima, Takao Hinamoto
    Discrete optimization for error feedback network using lower bound estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:508-511 [Conf]
  129. Chia-Yu Yao, Chiang-Ju Chien
    Design of a square-root-raised-cosine FIR filter by a recursive method. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:512-515 [Conf]
  130. Jinxin Hao, Gang Li, Jun Wu
    Pole deviation analysis for digital systems based on second order perturbation theory [digital filter example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:516-519 [Conf]
  131. Ling Cen, Yong Lian
    A hybrid GA for the design of multiplication-free frequency response masking filters [FIR digital filters]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:520-523 [Conf]
  132. Dirk S. Waldhauser, Christoph Saas, Josef A. Nossek
    Pulse shaping with bireciprocal wave digital lattice filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:524-527 [Conf]
  133. Masahide Abe, Hiroki Arai, Masayuki Kawamata
    Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:528-531 [Conf]
  134. Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
    A novel 2D filter design methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:532-535 [Conf]
  135. Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster
    Synthesis of reconfigurable multiplier blocks: part I - fundamentals. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:536-539 [Conf]
  136. Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster
    Synthesis of reconfigurable multiplier blocks: part - II algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:540-543 [Conf]
  137. Li-Hsun Chen, Oscal T.-C. Chen
    A hardware-efficient FIR architecture with input-data and tap folding. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:544-547 [Conf]
  138. Grace Y. Cho, Louis G. Johnson, Michael A. Soderstrand
    Residue number system implementations of complex heterodyne tunable filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:548-551 [Conf]
  139. Ashok Kumar, J. Luis Tecpanecatl-Xihuitl, Magdy A. Bayoumi
    Low complexity decimation filter for multi-standard digital receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:552-555 [Conf]
  140. Glen W. Mabey, Tamal Bose, Mei Chen
    Stability of a shift-variant 2-D state-space digital filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:556-559 [Conf]
  141. Chun-Chi Chen, Wen-Fu Lu, Chin-Chung Tsai, Poki Chen
    A time-to-digital-converter-based CMOS smart temperature sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:560-563 [Conf]
  142. Takashi Yoshida, Arimitsu Yokota, Hideki Kashiyama, Takayuki Hamamoto
    High-speed sensing system for depth estimation based on depth-from-focus by using smart imager. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:564-567 [Conf]
  143. J. L. D. Gonzalez, D. Sadowski, Karan V. I. S. Kaler, Martin P. Mintchev, Orly Yadid-Pecht
    A CMOS imager for light blobs detection and processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:568-571 [Conf]
  144. Fabrizio De Nisi, David Stoppa, Mauro Scandiuzzo, Lorenzo Gonzo, Lucio Pancheri, Gian-Franco Dalla Betta
    Design of electro-optical demodulating pixel in CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:572-575 [Conf]
  145. Shengke Zeng, John R. Powers, Larry L. Jackson, David L. Conover
    Digital measurement of human proximity to electrical power circuit by a novel amplitude-shift-keying radio-frequency receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:576-579 [Conf]
  146. Alexander Fish, Evgeny Avner, Orly Yadid-Pecht
    Low-power global/rolling shutter image sensors in silicon on sapphire technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:580-583 [Conf]
  147. Youngbok Kim, Anuj Agarwal, Sameer R. Sonkusale
    Low power current mode ADC for CMOS sensor IC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:584-587 [Conf]
  148. Vadim Alexander Milirud, Leonid Fleshel, Wenjing Zhang, Graham A. Jullien, Orly Yadid-Pecht
    A wide dynamic range CMOS active pixel sensor with frame difference. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:588-591 [Conf]
  149. Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De
    Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:592-595 [Conf]
  150. Guoqing Chen, Eby G. Friedman
    Low power repeaters driving RLC interconnects with delay and bandwidth constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:596-599 [Conf]
  151. Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Low-leakage repeaters for NoC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:600-603 [Conf]
  152. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
    Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:604-607 [Conf]
  153. Vidyasagar Nookala, Sachin S. Sapatnekar
    Designing optimized pipelined global interconnects: algorithms and methodology impact. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:608-611 [Conf]
  154. Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernandez, Eby G. Friedman
    Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:612-615 [Conf]
  155. Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi
    Battery-aware dynamic voltage scaling in multiprocessor embedded system. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:616-619 [Conf]
  156. Mikhail Popovich, Eby G. Friedman
    Noise coupling in multi-voltage power distribution systems with decoupling capacitors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:620-623 [Conf]
  157. Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale
    A 16-bit low-power microcontroller with monolithic MEMS-LC clocking. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:624-627 [Conf]
  158. Yuichi Nakamura, Takeshi Yoshimura
    A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:628-631 [Conf]
  159. Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara
    An LSI system with locked in temperature insensitive state achieved by using body bias technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:632-635 [Conf]
  160. Ming Zhang, Naresh R. Shanbhag
    An energy-efficient circuit technique for single event transient noise-tolerance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:636-639 [Conf]
  161. Chi-Fu Huang, Li-Chu Lo, Yu-Chee Tseng, Wen-Tsuen Chen
    Decentralized energy-conserving and coverage-preserving protocols for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:640-643 [Conf]
  162. Eugenio Culurciello, Thiago Teixeira, Andreas G. Andreou
    Event-based imaging with active illumination in sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:644-647 [Conf]
  163. Niwat Thepvilojanapong, Yoshito Tobe, Kaoru Sezaki
    On the construction of efficient data gathering tree in wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:648-651 [Conf]
  164. Cesare Alippi, Alan Mottarella, Giovanni Vanini
    A RF map-based localization algorithm for indoor environments. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:652-655 [Conf]
  165. Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
    A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:656-659 [Conf]
  166. Qiang Liu, Dong Tong, Xu Cheng
    Non-interleaving architecture for hardware implementation of modular multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:660-663 [Conf]
  167. Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
    A new design method to modulo 2/sup n/-1 squaring. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:664-667 [Conf]
  168. James E. Stine, Christopher R. Babb, Vibhuti B. Dave
    Constant addition utilizing flagged prefix structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:668-671 [Conf]
  169. Kei-Yong Khoo, Alan N. Willson Jr.
    Efficient VLSI implementation of N/N integer division. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:672-675 [Conf]
  170. Ge Zhang, Zichu Qi, Weiwu Hu
    A novel design of leading zero anticipation circuit with parallel error detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:676-679 [Conf]
  171. Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
    High-level synthesis under I/O timing and memory constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:680-683 [Conf]
  172. Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan
    A low power scheduling method using dual V/sub dd/ and dual V/sub th/. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:684-687 [Conf]
  173. Ling Wang, Yingtao Jiang, Yu Zhang, Ru Chen
    A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:688-691 [Conf]
  174. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    A heuristic approach for multiple restricted multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:692-695 [Conf]
  175. Junjuan Xu, Jason Cong, Xu Cheng
    Lower-bound estimation for multi-bitwidth scheduling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:696-699 [Conf]
  176. Koji Ohashi, Mineo Kaneko
    Statistical schedule length analysis in asynchronous datapath synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:700-703 [Conf]
  177. Antti Heiskanen, Timo Rahkonen
    Comparison of two class E amplifiers for EER transmitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:704-707 [Conf]
  178. Tadashi Suetsugu, Marian K. Kazimierczuk
    Steady-state behavior of class E amplifier outside designed conditions. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:708-711 [Conf]
  179. Tadashi Suetsugu, Marian K. Kazimierczuk
    Voltage-clamped class E amplifier with transmission-line transformer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:712-715 [Conf]
  180. Siu Chung Wong, Chi K. Michael Tse
    Optimum design of very low distortion class E power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:716-719 [Conf]
  181. Hiroyuki Hase, Hiroo Sekiya, Jianming Lu, Takashi Yahagi
    Resonant DC/DC converter with class E oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:720-723 [Conf]
  182. Alain Salles, Bruno Estibals, David Bourrier, Corinne Alonso
    Planar inductors with interleaved conductors for integrated power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:724-727 [Conf]
  183. Aleksandra Rankov, Esther Rodríguez-Villegas, Michael J. Lee
    A novel correlated double sampling poly-Si circuit for readout systems in large area X-ray sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:728-731 [Conf]
  184. T. Lehmann, Y. Moghe
    On-chip active power rectifiers for biomedical applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:732-735 [Conf]
  185. Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng
    A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:736-739 [Conf]
  186. Sunyoung Kim, Jae-Youl Lee, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo
    A 0.9-V 67-µW analog front-end using adaptive-SNR technique for digital hearing aid. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:740-743 [Conf]
  187. Iasonas F. Triantis, Andreas Demosthenous
    A BiCMOS ENG amplifier with high SIR output. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:744-747 [Conf]
  188. Robert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter Langlois, Nick Donaldson
    10-channel very low noise ENG amplifier system using CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:748-751 [Conf]
  189. Toshiya Mashima, Takanori Fukuoka, Satoshi Taoka, Toshimasa Watanabe
    Minimum augmentation to bi-connect specified vertices of a graph with upper bounds on vertex-degree. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:752-755 [Conf]
  190. Mamoru Sakamoto, Toshiyuki Miyamoto, Sadatoshi Kumagai
    A modeling method of a rule based control system with hierarchical Petri net. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:756-759 [Conf]
  191. Atsushi Ohta, Kohkichi Tsuji, Tomiji Hisamura
    Minimal time reachability problem of some subclasses of timed Petri nets. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:760-763 [Conf]
  192. Kai-Sheng Lu, Guo-Zhang Gao
    The node voltage equations and structural conditions of observability for RLC networks over F(z). [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:764-767 [Conf]
  193. Tetsuo Nishi, Masato Ogata
    Graph-theoretic approach to the design of four-switch DC-DC converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:768-771 [Conf]
  194. Sastry Mks
    Simplified algorithm to determine break point realys and relay coordination based on network topology [for realys read relays]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:772-775 [Conf]
  195. Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D'Amico, Andrea Baschirotto
    A low-distortion 1.2 V DAC+filter for transmitters in wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:776-779 [Conf]
  196. Po-Ming Lee, Hung-Yi Chen
    Adjustable gamma correction circuit for TFT LCD. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:780-783 [Conf]
  197. Beatriz Olleta, Hanjun Jiang, Degang Chen, Randall L. Geiger
    A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:784-787 [Conf]
  198. Georgi I. Radulov, Patrick J. Quinn, J. A. Hegt, Arthur H. M. van Roermund
    A start-up calibration method for generic current-steering D/A converters with optimal area solution. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:788-791 [Conf]
  199. Zhongjun Yu, Degang Chen, Randall L. Geiger, Ioannis Papantonopoulos
    Pipeline ADC linearity testing with dramatically reduced data capture time. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:792-795 [Conf]
  200. João Goes, Nuno F. Paulino, G. Evans
    On-chip built-in self-test of video-rate ADCs using Gaussian noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:796-799 [Conf]
  201. Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
    A 0.18µm CMOS low-noise elliptic low-pass continuous-time filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:800-803 [Conf]
  202. Shu-Hui Tu, J. Neil Ross
    Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum components. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:804-807 [Conf]
  203. Drazen Jurisic, Neven Mijat, George S. Moschytz
    Low-sensitivity active-RC filters using impedance tapering of symmetrical bridged-T and twin-T networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:808-811 [Conf]
  204. Tomoyuki Tanaka, Sungwoo Cha, Shinsaku Shimizu, Tsukasa Ida, Hiroaki Ishihara, Toshimasa Matsuoka, Kenji Taniguchi, Akashi Sugimori, Hiroki Hihara
    A widely tunable Gm-C filter using tail current offset in two differential pairs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:812-815 [Conf]
  205. S. Hirano, A. Sato, T. Kitamura
    A comparison approach of lowpass type wave active filter using unified circuit block. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:816-819 [Conf]
  206. G. Chandra, Preetam Tadeparthy, P. Easwaran
    Single amplifier bi-quadratic filter topologies in transimpedance configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:820-823 [Conf]
  207. Chien-Cheng Tseng, Tsung-Ming Hwang
    Quantum circuit design of discrete Hartley transform using recursive decomposition formula. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:824-827 [Conf]
  208. Chien-Cheng Tseng, Tsung-Ming Hwang
    Quantum circuit design of 8×8 discrete cosine transform using its fast computation flow graph. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:828-831 [Conf]
  209. Magdy T. Hanna, N. P. A. Seif, W. A. E. M. Ahmed
    Hermite-Gaussian-like eigenvectors of the DFT matrix generated by the eigenanalysis of an almost tridiagonal matrix. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:832-835 [Conf]
  210. Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy
    An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:836-839 [Conf]
  211. Alfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek
    Design of wavelet filters based on digital complex allpass filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:840-843 [Conf]
  212. Liang Tao, Hon Keung Kwan
    Block time-recursive discrete Gabor transform implemented by unified parallel lattice structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:844-847 [Conf]
  213. Andreas Spanias, Venkatraman Atti
    Rate determination based on perceptual loudness. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:848-851 [Conf]
  214. Benny Sallberg, Mattias Dahl, Henrik Akesson, Ingvar Claesson
    A mixed analog-digital hybrid for speech enhancement purposes. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:852-855 [Conf]
  215. Hai Quang Dam, Sven Nordholm, Hai Huyen Dam, Siow Yong Low
    Adaptive beamformer for hands-free communication system in noisy environments. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:856-859 [Conf]
  216. Sourabh Ravindran, David V. Anderson
    Audio classification and scene recognition and for hearing aids. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:860-863 [Conf]
  217. Yu Shao, Chip-Hong Chang
    A versatile speech enhancement system based on perceptual wavelet denoising. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:864-867 [Conf]
  218. Abhijeet Sangwan, Wei-Ping Zhu, M. Omair Ahmad
    Improved voice activity detection via contextual information and noise suppression. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:868-871 [Conf]
  219. Hiroshi Fujisaki, Gerhard Keller
    Approximations for bit error probabilities in SSMA communication systems using spreading sequences of Markov chains. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:872-875 [Conf]
  220. Ji Yao, Anthony J. Lawrance
    Optimal spreading in multi-user non-coherent binary chaos-shift-keying communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:876-879 [Conf]
  221. Chengqing Li, Xinxiao Li, Shujun Li, Guanrong Chen
    Cryptanalysis of a multistage encryption system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:880-883 [Conf]
  222. Yutaka Jitsumatsu, Tohru Kohda
    Design of code-matched receiver for DS/CDMA communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:884-887 [Conf]
  223. Slobodan Kozic, Thomas Schimming
    Coded modulation based on higher dimensional chaotic maps. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:888-891 [Conf]
  224. Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
    Long period pseudo random bit generators derived from a discretized chaotic map. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:892-895 [Conf]
  225. Haiyan Shu, Lap-Pui Chau
    Frame size selection in video downsizing transcoding application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:896-899 [Conf]
  226. Deepak P. Nayak, Dipan B. Mehta, Uday B. Desai
    A novel algorithm for reducing computational complexity of MC-DCT in frequency-domain video transcoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:900-903 [Conf]
  227. Viet Anh Nguyen, Yap-Peng Tan
    Efficient video transcoding between H.263 and H.264/AVC standards. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:904-907 [Conf]
  228. Kai-Tat Fung, Wan-Chi Siu
    Low complexity H.263 to H.264 video transcoding using motion vector decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:908-911 [Conf]
  229. Mei Kodama, Shunya Suzuki
    Consideration of transcoding using updatable scalability for selective quality video content delivery method. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:912-915 [Conf]
  230. Carlos Salazar-Lazaro, Trac D. Tran
    Flexible resizing algorithms for video transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:916-919 [Conf]
  231. Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue
    A low-power, 20-Gb/s continuous-time adaptive passive equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:920-923 [Conf]
  232. Norbert Neurohr, Matthias Schoebinger, Edoardo Prete, Anthony Sanders
    Adaptive decision-feedback equalization for band-limited high-speed serial links. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:924-927 [Conf]
  233. Junhua Tian, Bo Shen, Zheng Li, Jianing Su, Qianling Zhang
    Joint carrier recovery and adaptive equalization for high-order QAM. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:928-931 [Conf]
  234. Miguel A. Melgarejo, Fredy Olarte, Pedro Ladino
    Hardware realization of fuzzy adaptive filters for non linear channel equalization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:932-935 [Conf]
  235. Anthony Chan Carusone
    Jitter equalization for binary baseband communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:936-939 [Conf]
  236. Ting-An Lin, Chen-Yi Lee
    Predictive equalizer design for DVB-T system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:940-943 [Conf]
  237. Jeong-Hyu Yang, Chang-Su Kim, Sang-Uk Lee
    Progressive coding of 3D dynamic mesh sequences using spatiotemporal decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:944-947 [Conf]
  238. Jingliang Peng, Sheng Yang, C. C. Jay Kuo
    Progressive lossless 3D mesh encoder with octree-based space partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:948-951 [Conf]
  239. Hao-Song Kong, Anthony Vetro, Toshihiko Hata, Naoki Kuwahara
    Fast region-of-interest transcoding for JPEG 2000 images. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:952-955 [Conf]
  240. Jae-Young Sim, Sang-Uk Lee, Chang-Su Kim
    Construction of regular 3D point clouds using octree partitioning and resampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:956-959 [Conf]
  241. Dong Wang, Cedric Nishan Canagarajah, David R. Bull
    Slice group based multiple description video coding with three motion compensation loops. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:960-963 [Conf]
  242. Peng Wang, Rui Cai, Shi-Qiang Yang
    Improving classification of video shots using information-theoretic co-clustering. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:964-967 [Conf]
  243. Shunsuke Koshita, Masahide Abe, Masayuki Kawamata
    The upper bound of the second-order modes of linear state-space systems [digital filter example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:968-971 [Conf]
  244. Shunsuke Koshita, Masahide Abe, Masayuki Kawamata
    A novel property of the second-order modes of discrete-time systems under variable transformation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:972-975 [Conf]
  245. Aziz S. Inan, Peter M. Osterberg
    Special singularity integrals encountered in electric circuits [RLC circuit examples]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:976-979 [Conf]
  246. Alexei S. Adalev, Nikolai V. Korovkin, Masashi Hayakawa
    Identification of electric circuits: problems and methods of solution accuracy enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:980-983 [Conf]
  247. Luis Nero Alves, Rui L. Aguiar
    On the effect of time delays in negative feedback amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:984-987 [Conf]
  248. Svante Signell
    Jittered uniform sampling - examples. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:988-991 [Conf]
  249. Barbara Cannas, Alessandra Fanni, Augusto Montisci
    Testability evaluation for analog linear circuits via transfer function analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:992-995 [Conf]
  250. Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch
    Synthesis of MITE log-domain filters with unique operating points. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:996-999 [Conf]
  251. Soliman A. Mahmoud
    Low voltage high current gain CMOS digitally controlled fully differential CCII [variable gain amplifier application example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1000-1003 [Conf]
  252. Boonchai Boonchu, Wanlop Surakampontorn
    A new NMOS four-quadrant analog multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1004-1007 [Conf]
  253. Juan M. Carrillo, J. Francisco Duque-Carrillo, Antonio B. Torralba, Ramón González Carvajal
    Class-AB rail-to-rail CMOS analog buffer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1008-1011 [Conf]
  254. Eduardo Rapoport, Fernando Antonio Pinto Baruqui, Antonio Petraglia
    IC design of an analog tunable crossover network. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1012-1015 [Conf]
  255. Varakorn Kasemsuwan, Teerawat Arthansiri, Hyung Keun Ahn
    A ± 1.5 V high frequency four quadrant current multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1016-1019 [Conf]
  256. Fábio A. Pereira, Mário C. G. de Oliveira, Ana Isabela Araújo Cunha
    CMOS analog current-mode multiplier based on the advanced compact MOSFET model. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1020-1023 [Conf]
  257. T. Yasuda
    On-chip temperature sensor with high tolerance for process and temperature variation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1024-1027 [Conf]
  258. Yaxiong Zhang, Alister Hamilton
    A current mode Palmo cell for programmable analogue signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1028-1031 [Conf]
  259. Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu
    A memory-reduced log-MAP kernel for turbo decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1032-1035 [Conf]
  260. Hanho Lee
    An ultra high-speed Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1036-1039 [Conf]
  261. Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang
    A new low-power turbo decoder using HDA-DHDD stopping iteration. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1040-1043 [Conf]
  262. Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli
    Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1044-1047 [Conf]
  263. Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay
    Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1048-1050 [Conf]
  264. Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed
    A new reconfigurable modem architecture for 3G multi-standard wireless communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1051-1054 [Conf]
  265. Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang
    A 12.5 Gbps CMOS input sampler for serial link receiver front end. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1055-1058 [Conf]
  266. Zeynep Toprak Deniz, Yusuf Leblebici
    Low-power current mode logic for improved DPA-resistance in embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1059-1062 [Conf]
  267. Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim
    A new level-up shifter for high speed and wide range interface in ultra deep sub-micron. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1063-1065 [Conf]
  268. Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
    A novel CMOS logic style with data independent power consumption. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1066-1069 [Conf]
  269. Kuo-Hsing Cheng, Chen-Lung Wu, Yu-lung Lo, Chia-Wei Su
    A phase-detect synchronous mirror delay for clock skew-compensation circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1070-1073 [Conf]
  270. I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu
    A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1074-1077 [Conf]
  271. Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
    A linear model for high-level delay estimation in VDSM on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1078-1081 [Conf]
  272. Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam
    A closed-form delay formula for on-chip RLC interconnects in current-mode signaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1082-1085 [Conf]
  273. Soo-Chang Pei, Meng-Ping Kao
    Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matrices. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1086-1089 [Conf]
  274. Truong T. Nguyen, Soontorn Oraintara
    Multidimensional filter banks design by direct optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1090-1093 [Conf]
  275. S. C. Chan, S. S. Yin
    On the theory and design of a class of PR causal-stable IIR non-uniform recombination cosine modulated filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1094-1097 [Conf]
  276. Robert Bregovic, Tapio Saramäki
    Design of two-channels FIR filterbanks with rational sampling factors using the FRM technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1098-1101 [Conf]
  277. Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
    Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1102-1105 [Conf]
  278. Pilar Martín-Martín, Fernando Cruz-Roldán, Tapio Saramäki
    : Optimized transmultiplexers for multirate systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1106-1109 [Conf]
  279. Truong T. Nguyen, Soontorn Oraintara
    A class of directional filter banks [image processing applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1110-1113 [Conf]
  280. Mariane R. Petraglia, Paulo B. Batalheiro
    Filter bank design for an adaptive subband structure with critical sampling using a new adaptation scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1114-1117 [Conf]
  281. Hau-Jie Liang, Shuenn-Shyang Wang
    Architectural design of fractal image coder based on kick-out condition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1118-1121 [Conf]
  282. Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal
    Dictionary-based program compression on transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1122-1125 [Conf]
  283. Bo Fang, Guobin Shen, Shipeng Li, Huifang Chen
    Techniques for efficient DCT/IDCT implementation on generic GPU. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1126-1129 [Conf]
  284. Yun Yang, Wenqing Zhao, Yasuaki Inoue
    High-performance systolic arrays for band matrix multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1130-1133 [Conf]
  285. Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen
    Block-level parallel processing for scaling evenly divisible frames. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1134-1137 [Conf]
  286. Daewook Kim, Manho Kim, Gerald E. Sobelman
    Parallel FFT computation with a CDMA-based network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1138-1141 [Conf]
  287. Hongtu Jiang, Håkan Ardõ, Viktor Öwall
    Hardware accelerator design for video segmentation with multi-modal background modelling. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1142-1145 [Conf]
  288. Saed Samadi, M. Omair Ahmad, M. N. S. Swamy
    Multiplier-free structures for exact generation of natural powers of integers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1146-1149 [Conf]
  289. Ching-Yuan Yang, Yu Lee
    A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1150-1153 [Conf]
  290. Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, R. Dlugosz, A. Dabrowski
    3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1154-1157 [Conf]
  291. Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
    A 0.18µm CMOS transceiver design for high-speed backplane data communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1158-1161 [Conf]
  292. Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue
    A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1162-1165 [Conf]
  293. Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas
    An electrically adjustable distributed pulse shaping filter for 40 Gbit/s optical links. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1166-1169 [Conf]
  294. Mona M. Hella, Richard Panock
    Dual-loop control of laser drivers for 3.125GHz optical transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1170-1173 [Conf]
  295. Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
    A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1174-1177 [Conf]
  296. Vasanth Kakani, Foster F. Dai, Richard C. Jaeger
    An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1178-1181 [Conf]
  297. Kun-Hsien Lin, Ming-Dou Ker
    ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1182-1185 [Conf]
  298. Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu
    A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1190-1193 [Conf]
  299. Markus P. J. Mergens, Geert Wybo, Bart Keppens, Benjamin Van Camp, Frederic De Ranter, Koen G. Verhaege, John Armer, Phillip Jozwiak, Christian C. Russ
    ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1194-1197 [Conf]
  300. Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong
    A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1198-1201 [Conf]
  301. Elyse Rosenbaum, Sami Hyvonen
    On-chip ESD protection for RF I/Os: devices, circuits and models. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1202-1205 [Conf]
  302. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A methodology for partitioning DSP applications in hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1206-1209 [Conf]
  303. Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
    A new approach based on LFF for optimization of dynamic hardware reconfigurations. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1210-1213 [Conf]
  304. Minoru Watanabe, Fuminori Kobayashi
    A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1214-1217 [Conf]
  305. Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
    Pipelining technique for energy-aware datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1218-1221 [Conf]
  306. Somsubhra Mondal, Seda Ogrenci Memik
    A low power FPGA routing architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1222-1225 [Conf]
  307. Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan
    Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1226-1229 [Conf]
  308. Zhi Zhou, Shijun Sun, Shawmin Lei, Ming-Ting Sun
    Motion information and coding mode reuse for MPEG-2 to H.264 transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1230-1233 [Conf]
  309. Yeping Su, Jun Xin, Anthony Vetro, Huifang Sun
    Efficient MPEG-2 to H.264/AVC intra transcoding in transform-domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1234-1237 [Conf]
  310. You-Neng Xiao, Hong Lu, Xiangyang Xue, Viet Anh Nguyen, Yap-Peng Tan
    Efficient rate control for MPEG-2 to H.264/AVC transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1238-1241 [Conf]
  311. Chen-Po Chang, Chia-Wen Lin
    R-D optimized quantization of H.264 SP-frames for bitstream switching under storage constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1242-1245 [Conf]
  312. Xiaoan Lu, Alexis Michael Tourapis, Peng Yin, Jill Boyce
    Fast mode decision and motion estimation for H.264 with a focus on MPEG-2/H.264 transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1246-1249 [Conf]
  313. Ching-Yung Lin, Belle L. Tseng
    Optimizing user expectations for video semantic filtering and abstraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1250-1253 [Conf]
  314. Lacina M. Coulibaly, H. J. Kadim
    Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1254-1257 [Conf]
  315. Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang
    An all-digital pulsewidth control loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1258-1261 [Conf]
  316. Hui Zhang, Pinaki Mazumder
    Design of a new sense amplifier flip-flop with improved power-delay-product. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1262-1265 [Conf]
  317. Davide Baderna, Alessandro Cabrini, Guido De Sandre, Francesco De Santis, Marco Pasotti, Andrea Rossini, Guido Torelli
    A 1.2 V sense amplifier for high-performance embeddable NOR flash memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1266-1269 [Conf]
  318. Ferdinando Bedeschi, Edoardo Bonizzoni, Giulio Casagrande, Roberto Gastaldi, Claudio Resta, Guido Torelli, Daniele ZelLa
    SET and RESET pulse characterization in BJT-selected phase-change memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1270-1273 [Conf]
  319. Jing Chen, Miao Li, Tad A. Kwasniewski
    Decision feedback equalization for high-speed backplane data communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1274-1277 [Conf]
  320. Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai
    Interconnect model reductions by using the AORA algorithm with considering the adjoint network. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1278-1281 [Conf]
  321. Hua Tang, Alex Doboli
    Parameter domain pruning for improving convergence of synthesis algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1282-1285 [Conf]
  322. Fernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli
    Enriching an analog platform for analog-to-digital converter design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1286-1289 [Conf]
  323. Alfred Tze-Mun Leung, Roni Khazaka
    Parametric model order reduction technique for design optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1290-1293 [Conf]
  324. Gülin Tulunay, Sina Balkir
    Design automation of single-ended LNAs using symbolic analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1294-1297 [Conf]
  325. Trent McConaghy, Georges G. E. Gielen
    Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1298-1301 [Conf]
  326. Vahid Yousefzadeh, Eduard Alarcón, Dragan Maksimovic
    Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1302-1305 [Conf]
  327. Shiyan Hu, Han Huang, Dariusz Czarkowski
    Hybrid trigonometric differential evolution for optimizing harmonic distribution. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1306-1309 [Conf]
  328. Boris Axelrod, Yefim Berkovich, Adrian Ioinovici
    Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up mode. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1310-1313 [Conf]
  329. Yushan Li, Dragan Maksimovic
    High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1314-1317 [Conf]
  330. Carlos Meza, Domingo Biel, Luis Martinez-Salamero, Francisco Guinjoan
    Boost-buck inverter variable structure control for grid-connected photovoltaic systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1318-1321 [Conf]
  331. Hirotaka Koizumi, Kosuke Kurokawa, Shinsaku Mori
    Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulses. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1322-1325 [Conf]
  332. Jingbo Yang, Meng Tong Tan, Joseph Sylvester Chang
    Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1326-1329 [Conf]
  333. Joachim Neves Rodrigues, Thomas Olsson, Leif Sörnmo, Viktor Öwall
    A dual-mode wavelet based R-wave detector using single-Vt for leakage reduction [cardiac pacemaker applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1330-1333 [Conf]
  334. Hakan Gürkan, Ümit Güz, B. Siddik Yarman
    An efficient ECG data compression technique based on predefined signature and envelope vector banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1334-1337 [Conf]
  335. Qiyue Zou, Zhiping Lin, Raimund J. Ober
    The CRLB for bilinear systems and its biomedical applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1338-1341 [Conf]
  336. Kyle E. Thomson, Theo Shlien, Yasir Suhail, Karim G. Oweiss
    Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1342-1345 [Conf]
  337. Yehya H. Ghallab, Wael M. Badawy
    A novel CMOS lab-on-a-chip for biomedical applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1346-1349 [Conf]
  338. Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu
    Probabilistic congestion prediction in hierarchical quad-grid model. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1350-1353 [Conf]
  339. Akira Matsubayashi
    Small congestion embedding of separable graphs into grids of the same size. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1354-1357 [Conf]
  340. Toshinori Yamada, Hiroyuki Kawakita, Tadashi Nishiyama, Shuichi Ueno
    On VLSI decompositions for d-ary de Bruijn graphs (extended abstract). [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1358-1361 [Conf]
  341. Makoto Fujimoto, Daisuke Takafuji, Toshimasa Watanabe
    Approximation algorithms for the rectilinear Steiner tree problem with obstacles. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1362-1365 [Conf]
  342. Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen
    Wiring area optimization in floorplan-aware hierarchical power grids. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1366-1369 [Conf]
  343. Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee
    Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1370-1373 [Conf]
  344. Jen-Lin Fan, Jieh-Tsorng Wu
    A robust background calibration technique for switched-capacitor pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1374-1377 [Conf]
  345. Le Jin, Degang Chen, Randall L. Geiger
    A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1378-1381 [Conf]
  346. Ding-Lan Shen, Tai-Cheng Lee
    A linear-approximation technique for digitally-calibrated pipelined A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1382-1385 [Conf]
  347. Cristiano Azzolini, Andrea Boni, Alessio Facen, Matteo Parenti, Davide Vecchi
    Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1386-1389 [Conf]
  348. Oscar E. Agazzi, Venu Gopinathan
    Background calibration of interleaved analog to digital converters for high-speed communications using interleaved timing recovery techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1390-1393 [Conf]
  349. Christian Vogel, Dieter Draxelmayr, Gernot Kubin
    Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1394-1397 [Conf]
  350. Phil Corbishley, Esther Rodríguez-Villegas
    Programmable switched-current floating-gate cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1398-1401 [Conf]
  351. Daeik D. Kim, Martin A. Brooke
    Time-interleaved switched-capacitor filter for reconfigurable triple-band delta-sigma converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1402-1405 [Conf]
  352. Hooman Kaabi, M. R. Jahed Motlagh, Ahmad Ayatollahi
    A novel current-conveyor-based switched-capacitor integrator. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1406-1408 [Conf]
  353. Hashem Zare-Hoseini, Omid Shoaei, Izzet Kale
    A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1409-1412 [Conf]
  354. Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider
    Inverter-based switched current circuit for very low-voltage and low-power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1413-1416 [Conf]
  355. Hold Omid Rajaee, Mehrdad Sharif Bakhtiar
    A high speed, high resolution, low voltage current mode sample and hold. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1417-1420 [Conf]
  356. Liang Chen, Qiang Hua, H. K. Kwan
    An improved algorithm for maximum-likelihood based approach for a multitarget tracking problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1421-1424 [Conf]
  357. Andrzej Tarczynski, Dongdong Qu
    Optimal periodic sampling sequences for nearly-alias-free digital signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1425-1428 [Conf]
  358. Tuomo W. Pirinen
    Normalized confidence factors for robust direction of arrival estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1429-1432 [Conf]
  359. Wei Xing Zheng
    An efficient method for estimation of autoregressive signals in noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1433-1436 [Conf]
  360. Zaihe Yu, Yun Q. Shi, Wei Su
    Symbol-rate estimation based on filter bank. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1437-1440 [Conf]
  361. Nanyan Y. Wang, Panajotis Agathoklis, Andreas Antoniou
    Pilot-aided DOA estimation for CDMA communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1441-1444 [Conf]
  362. Yasuhiro Takahashi, Michio Yokoyama
    New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1445-1448 [Conf]
  363. Kenny Johansson, Oscar Gustafsson, Lars Wanhammar
    Implementation of low-complexity FIR filters using serial arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1449-1452 [Conf]
  364. Oscar Gustafsson, Henrik Ohlsson
    A low power decimation filter architecture for high-speed single-bit sigma-delta modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1453-1456 [Conf]
  365. Arjuna Madanayake, Leonard T. Bruton
    A high performance distributed-parallel-processor architecture for 3D IIR digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1457-1460 [Conf]
  366. Chengjun Zhang, Chunyan Wang, M. Omair Ahmad
    A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1461-1464 [Conf]
  367. Moonseok Kang, Wonyong Sung
    Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1465-1468 [Conf]
  368. Dong Dai, Yue Ma, Chi K. Michael Tse
    Horseshoes, homoclinic connections and global chaos in current-mode controlled DC/DC converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1469-1472 [Conf]
  369. Simin Yu, Jinhu Lu, Henry Leung, Guanrong Chen
    N-scroll chaotic attractors from a general jerk circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1473-1476 [Conf]
  370. A. Kato, T. Kohda
    Solvable 2-dimensional rational chaotic map defined by Jacobian elliptic functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1477-1480 [Conf]
  371. Yoko Uwate, Yoshifumi Nishio
    Back propagation learning of neural networks with chaotically-selected affordable neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1481-1484 [Conf]
  372. Fabiola Angulo, Mario di Bernardo
    On two-parameter non-smooth bifurcations in power converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1485-1488 [Conf]
  373. M. Balestra, Marco Lazzarini, Gianluca Setti, Riccardo Rovatti
    Experimental performance evaluation of a low-EMI chaos-based current-programmed DC/DC boost converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1489-1492 [Conf]
  374. Chen-Fu Lin, Jin-Jang Leou
    An adaptive fast full search motion estimation algorithm for H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1493-1496 [Conf]
  375. Chen Chen, Ping-Hao Wu, Homer H. Chen
    Transform-domain intra prediction for H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1497-1500 [Conf]
  376. Minqiang Jiang, Nam Ling
    An improved frame and macroblock layer bit allocation scheme for H.264 rate control. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1501-1504 [Conf]
  377. Shu-Fa Lin, Meng-Ting Lu, Ming-yu Chen, Chia-Ho Pan
    Fast multi-frame motion estimation for H.264 and its applications to complexity-aware streaming. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1505-1508 [Conf]
  378. Chao-Chung Cheng, Tian-Sheuan Chang
    Fast three step intra prediction algorithm for 4×4 blocks in H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1509-1512 [Conf]
  379. Chi-Wai Lam, Lai-Man Po
    Fast block motion estimation with early acceptance technique in H.264/JVT. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1513-1516 [Conf]
  380. Takayuki Yamashita, Kazuhisa Haeiwa, Toshihiro Negishi, Izuru Murasaki, Yoshikazu Toba, Masatoshi Onizawa
    Development of a microwave receiving and transmission system using an optical modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1517-1520 [Conf]
  381. Jonathan Sewter, Anthony Chan Carusone
    A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1521-1524 [Conf]
  382. Hai Qi Liu, Wang Ling Goh, L. Siek
    A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1525-1528 [Conf]
  383. Ju-Hyoung Mun, Sung Min Park, Myung-Ryong Nam
    Four-channel CMOS photoreceiver array for parallel optical interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1529-1532 [Conf]
  384. Ho-Ting Wu, Kai-Wei Ke, Wang-Rong Chang, Hui-Tang Lin
    A switched delay line based optical switch architecture with a bypass line. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1533-1536 [Conf]
  385. Euhan Chong, Khoman Phang
    A 400Mbps CMOS spatially-modulated photoreceiver for optical storage. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1537-1540 [Conf]
  386. Ka-Man Wong, Kwok-Wai Cheung, Lai-Man Po
    MIRROR: an interactive content based image retrieval system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1541-1544 [Conf]
  387. Yinqing Zhao, C. C. Jay Kuo
    Scheduling design for distributed video-on-demand servers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1545-1548 [Conf]
  388. Liuhong Liang, Hong Lu, Xiangyang Xue, Yap-Peng Tan
    Program segmentation for TV videos. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1549-1552 [Conf]
  389. Huang-Chia Shih, Chung-Lin Huang
    Content-based scalable sports video retrieval system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1553-1556 [Conf]
  390. Jun-Hua Han, De-Shuang Huang
    A novel BP-based image retrieval system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1557-1560 [Conf]
  391. Vadim Ivanov, Igor M. Filanovsky
    A 110 dB CMRR/PSRR/gain CMOS operational amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1561-1564 [Conf]
  392. Mohammad Yavari, Omid Shoaei, Francesco Svelto
    Hybrid cascode compensation for two-stage CMOS operational amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1565-1568 [Conf]
  393. A. D. Grasso, Salvatore Pennisi
    High-performance CMOS pseudo-differential amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1569-1572 [Conf]
  394. Salvatore Pennisi
    High-performance CMOS current feedback operational amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1573-1576 [Conf]
  395. Khanittha Kaewdang, Wanlop Surakampontorn, Nobuo Fujii
    A design of controllable [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1577-1580 [Conf]
  396. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1581-1584 [Conf]
  397. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1585-1588 [Conf]
  398. Takao Tsukutani, Yasuaki Sumi, Masami Higashimura, Yutaka Fukui
    Current-mode universal biquad circuit using MO-OTAs and DO-CCII. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1589-1592 [Conf]
  399. T. Halvorsrod, O. Birkenes, C. Eichrodt
    A low-power method adding continuous variable gain to amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1593-1596 [Conf]
  400. E. D. Totev, Chris J. M. Verhoeven
    Design consideration for lowering sensitivity to out of band interference of negative feedback amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1597-1600 [Conf]
  401. Yanjie Wang, Rabin Raut
    A 2.4 GHz 82 dB-Omega fully differential CMOS transimpedance amplifier for optical receiver based on wide-swing cascode topology. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1601-1605 [Conf]
  402. Apisak Worapishet, I. Roopkom
    Cascaded double-stage configuration for high-performance broadband amplification in CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1606-1609 [Conf]
  403. Koen van Hartingsveldt, Chris J. M. Verhoeven, J. Willms
    Influence of frequency compensation on the linearity of negative feedback amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1610-1613 [Conf]
  404. Wacharapol Pongpalit, Varakorn Kasemsuwan, Hyungkeun Ahn
    A 3 Gb/s 80 dB CMOS differential transimpedance amplifier for optical communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1614-1617 [Conf]
  405. Yu Lin, Vipul Katyal, Randall L. Geiger
    Power dependence of feedback amplifiers on opamp architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1618-1621 [Conf]
  406. Soliman A. Mahmoud, Mohammed A. Hashiesh, Ahmed M. Soliman
    Digitally controlled fully differential current conveyor: CMOS realization and applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1622-1625 [Conf]
  407. Subhadeep Roy
    A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1626-1629 [Conf]
  408. Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan
    A configurable dual moduli multi-operand modulo adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1630-1633 [Conf]
  409. Shahnam Khabiri, Maitham Shams
    An MCML four-bit ripple-carry adder design in 1 GHz range. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1634-1637 [Conf]
  410. Ming-Chen Wen, Sying-Jyan Wang, Yen-Nan Lin
    Low power parallel multiplier with column bypassing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1638-1641 [Conf]
  411. Jieh-Hwang Yen, Lan-Rong Dung, Chi-Yuan Shen
    Design of power-aware multiplier with graceful quality-power trade-offs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1642-1645 [Conf]
  412. Xiaoyao Liang, Akshay Athalye, Sangjin Hong
    Equalizing data-path for processing speed determination in block level pipelining. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1646-1649 [Conf]
  413. Ramy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi
    Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1650-1653 [Conf]
  414. Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson
    A low-leakage twin-precision multiplier using reconfigurable power gating. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1654-1657 [Conf]
  415. Lei Wang
    An energy-efficient skew compensation technique for high-speed skew-sensitive signaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1658-1661 [Conf]
  416. Donald M. Chiarulli, Jason D. Bakos, Joel R. Martin, Steven P. Levitan
    Area, power, and pin efficient bus transceiver using multi-bit-differential signaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1662-1665 [Conf]
  417. Behnam Amelifard, Ali Afzali-Kusha, Ahmad Khademzadeh
    Enhancing the efficiency of cluster voltage scaling technique for low-power application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1666-1669 [Conf]
  418. Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
    A low-power high-SFDR CMOS direct digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1670-1673 [Conf]
  419. A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani
    Domino logic with an efficient variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1674-1677 [Conf]
  420. Tadayoshi Enomoto, Nobuaki Kobayashi
    A low dynamic power and low leakage power CMOS square-root circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1678-1681 [Conf]
  421. Jianfeng Chen, Koksoon Phua, Louis Shue, Hanwu Sun
    A robust adaptive cross microphone array. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1682-1685 [Conf]
  422. Mohammed A. Khasawneh, Khaled A. Mayyas, R. M. Shalabi, Monther I. Haddad
    A combined TDA/FDA adaptive schema for stereophonic acoustic echo cancellation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1686-1689 [Conf]
  423. Rong-Jian Chen, Wen-Kai Lu, Jui-Lin Lai
    Image encryption using progressive cellular automata substitution and SCAN. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1690-1693 [Conf]
  424. Wei Xing Zheng
    Study of a least-squares type method for noisy FIR filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1694-1697 [Conf]
  425. Isao Nakanishi, Hiroyuki Sakamoto, Yoshio Itoh, Yutaka Fukui
    Optimal user weighting fusion in DWT domain on-line signature verification. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1698-1701 [Conf]
  426. Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi
    A hardware generator for multi-point distributed random variables. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1702-1705 [Conf]
  427. Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takashi Katagiri
    Direct-digital synthesis using delta-sigma modulated signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1706-1709 [Conf]
  428. Xinping Huang, Mario Caron
    Performance of a type-based digital predistorter for solid-state power amplifier linearization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1710-1713 [Conf]
  429. Hui Zhao, Kan Zheng, Wenbo Wang
    Diversity gain's influence on MIMO's detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1714-1717 [Conf]
  430. Deepali Arora, Panajotis Agathoklis
    Multiuser scheduling for downlink in multi-antenna wireless systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1718-1721 [Conf]
  431. Zhiguo Zhang, Shing-Chow Chan, Hui Cheng
    Robust adaptive channel estimation of OFDM systems in time-varying narrowband interference. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1722-1725 [Conf]
  432. Hoang-Yang Lu, Wen-Hsien Fang
    Joint frequency offset estimation and multiuser detection using genetic algorithm in MC-CDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1726-1729 [Conf]
  433. Yu-Hao Chang, Xiaoli Yu
    Reduced-rank antenna selection for MIMO DS-CDMA channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1730-1733 [Conf]
  434. Saman S. Abeysekera, Zhi Wang
    Performance of the pulse pair method with an optimal lag value for frequency estimation in fading channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1734-1737 [Conf]
  435. Dae-Ik Kim, Mikkel A. Thomas, Jeffrey J. Lillie, Karla S. Dennis, Benita M. Comeau, Martin A. Brooke, Nan M. Jokerst, Stephen E. Ralph, Clifford L. Henderson
    Integrated mixed-signal optoelectronic system-on-a-chip sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1738-1741 [Conf]
  436. Francisco Serra-Graells, Bertrand Misischi, Eduardo Casanueva, César Méndez, Lluís Terés
    A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1742-1745 [Conf]
  437. Xiaolong Wu, Jian Ma, Yingtao Jiang, Bingmei Fu, Wei Hang, Jinsuo Zhang, Ning Li
    Instrumentation of YSZ oxygen sensor calibration in liquid lead-bismuth eutectic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1746-1749 [Conf]
  438. Jianfeng Chen, Jianmin Zhang, Alvin Harvey Kam, Louis Shue
    An automatic acoustic bathroom monitoring system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1750-1753 [Conf]
  439. Yat-Fong Yung, Amine Bermak
    A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1754-1757 [Conf]
  440. Matti Kutila, Jouko Viitanen
    Sensor array for multiple emission gas measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1758-1761 [Conf]
  441. Lisa E. Hansen, Matthew M. W. Johnston, Denise M. Wilson
    Pulse-based interface circuits for SPR sensing systems [analyte concentration measurement]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1762-1765 [Conf]
  442. Christian Neeb, Michael J. Thul, Norbert Wehn
    Network-on-chip-centric approach to interleaving in high throughput channel decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1766-1769 [Conf]
  443. Axel Jantsch, Robert Lauter, Arseni Vitkovski
    Power analysis of link level and end-to-end data protection in networks on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1770-1773 [Conf]
  444. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh
    Effect of traffic localization on energy dissipation in NoC-based interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1774-1777 [Conf]
  445. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar
    A methodology for design, modeling, and analysis of networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1778-1781 [Conf]
  446. Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
    Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1782-1785 [Conf]
  447. Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi
    VLSI architecture based on packet data transfer scheme and its application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1786-1789 [Conf]
  448. Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen
    Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1790-1793 [Conf]
  449. Cao Wei, Mao Zhi Gang
    A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1794-1797 [Conf]
  450. Yi-Hau Chen, Ching-Yeh Chen, Liang-Gee Chen
    Architecture of global motion compensation for MPEG-4 advanced simple profile. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:1798-1801 [Conf]
  451. Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang
    Combined 2-D transform and quantization architectures for H.264 video coders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1802-1805 [Conf]
  452. N. Y. C. Chang, T. S. Chang
    Combined frame memory architecture for motion compensation in video decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1806-1809 [Conf]
  453. Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee
    An H.264/AVC decoder with 4×4-block level pipeline. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1810-1813 [Conf]
  454. Andrew G. Dempster, Malcolm D. Macleod
    Multiplication by two integers using the minimum number of adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1814-1817 [Conf]
  455. Ya Jun Yu, Yong Ching Lim
    Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1819-1822 [Conf]
  456. Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
    I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1823-1826 [Conf]
  457. Juha Yli-Kaakinen, Tapio Saramäki
    Design and implementation of multiplierless adjustable fractional-delay all-pass filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1827-1830 [Conf]
  458. Wu-Sheng Lu
    Design of FIR digital filters with discrete coefficients via convex relaxation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1831-1834 [Conf]
  459. Chao Cheng, Keshab K. Parhi
    Further complexity reduction of parallel FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1835-1838 [Conf]
  460. Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
    Glitch-free discretely programmable clock generation on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1839-1842 [Conf]
  461. Yan Zhang, Travis Blalock, Mircea R. Stan
    A three-level toggle-avoid bus signaling scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1843-1846 [Conf]
  462. Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun
    A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1847-1850 [Conf]
  463. Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
    A distributed FIFO scheme for on chip communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1851-1854 [Conf]
  464. Jan Doutreloigne, Miguel Vermandel, Herbert De Smet, André Van Calster
    A multifunctional high-voltage driver chip for low-power mobile display systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1855-1858 [Conf]
  465. Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
    Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1859-1862 [Conf]
  466. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
    Performance constrained floorplanning based on partial clustering [IC layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1863-1866 [Conf]
  467. Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee
    Wire-driven microarchitectural design space exploration. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1867-1870 [Conf]
  468. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    Integrated routing resource assignment for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1871-1874 [Conf]
  469. Yen-Tai Lai, Hsin-Ya Lai, Chia-Nan Yeh
    Placement for the reconfigurable datapath architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1875-1878 [Conf]
  470. Hao-Yueh Hsieh, Ting-Chi Wang
    Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1879-1882 [Conf]
  471. Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
    Fixed-outline floorplanning with constraints through instance augmentation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1883-1886 [Conf]
  472. Christian Falconi, Giancarlo Savone, Arnaldo D'Amico
    High light-load efficiency charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1887-1890 [Conf]
  473. Davide Baderna, Alessandro Cabrini, Guido Torelli, Marco Pasotti
    Efficiency comparison between doubler and Dickson charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1891-1894 [Conf]
  474. Wing-Hung Ki, Feng Su, Chi-Ying Tsui
    Charge redistribution loss consideration in optimal charge pump design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1895-1898 [Conf]
  475. T. Hasan, Torsten Lehmann, Chee Yee Kwok
    A 5V charge pump in a standard 1.8-V 0.18-µm CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1899-1902 [Conf]
  476. R. Arona, Edoardo Bonizzoni, Franco Maloberti, Guido Torelli
    Heap charge pump optimisation by a tapered architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1903-1906 [Conf]
  477. Feng Su, Wing-Hung Ki, Chi-Ying Tsui
    Gate control strategies for high efficiency charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1907-1910 [Conf]
  478. Minghua Shi, Amine Bermak, Sofiane Brahim-Belhouari
    Quantization errors in committee machine for gas sensor applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1911-1914 [Conf]
  479. Kazuhiro Shimonomura, Tetsuya Yagi
    A 100×100 pixels orientation-selective multi-chip vision system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1915-1918 [Conf]
  480. R. Jacob Vogelstein, Udayan Mallik, Eugenio Culurciello, Gert Cauwenberghs, Ralph Etienne-Cummings
    A real-time spike-domain sensory information processing system [image processing applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1919-1922 [Conf]
  481. Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
    Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1923-1926 [Conf]
  482. Yoshio Kon'no, Toshimichi Saito, Hiroyuki Torikai
    Rich spike-synchronization phenomena of pulse-coupled bifurcating neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1927-1931 [Conf]
  483. W. Aly-Mekawi, Ezz I. El-Masry
    Novel µ-power log-domain integrators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1932-1935 [Conf]
  484. Justin P. Abbott, Calvin Plett, John W. M. Rogers
    A low voltage CMOS multiplier for high frequency equalization. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1936-1939 [Conf]
  485. M. Kiyoyama, Michihisa Onoda, Yoshinobu Tanaka
    A low current consumption CMOS latched comparator for body-implanted chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1940-1943 [Conf]
  486. A. L. Dalcastangê, Sidnei Noceti Filho
    On the analog generation of pink noise from white noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1944-1947 [Conf]
  487. Baohua Wang, Pinaki Mazumder
    Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit models. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1948-1951 [Conf]
  488. Eric Lebel, Ali Assi, Mohamad Sawan
    Field programmable Gm-C array for wide frequency range bandpass filter applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1952-1955 [Conf]
  489. Patrick J. Quinn, Arthur H. M. van Roermund
    Accuracy limitations of pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1956-1959 [Conf]
  490. Byung Geun Lee, Shouli Yan
    A new ratio-independent A/D conversion technique for high-resolution pipeline A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1960-1963 [Conf]
  491. Patrick J. Quinn, Arthur H. M. van Roermund
    Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1964-1967 [Conf]
  492. Yu Lin, Vipul Katyal, Mark Schlarmann, Randall L. Geiger
    kT/C constrained optimization of power in pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1968-1971 [Conf]
  493. Hsin-Hung Ou, Bin-Da Liu
    A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1972-1975 [Conf]
  494. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Full calibration digital techniques for pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1976-1979 [Conf]
  495. David W. Graham, Paul D. Smith, Richard Ellis, Ravi Chawla, Paul E. Hasler
    A low-power, programmable bandpass filter section for higher-order filter-bank applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1980-1983 [Conf]
  496. Louie Pylarinos, Khoman Phang
    Low-voltage programmable gm-C filter for hearing aids using dynamic gate biasing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1984-1987 [Conf]
  497. Jader A. De Lima, Wouter A. Serdijn
    A compact nA/V CMOS triode-transconductor and its application to very-low frequency filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1988-1991 [Conf]
  498. Mykhaylo A. Teplechuk, John I. Sewell
    Wave log-domain filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1992-1995 [Conf]
  499. Mykhaylo A. Teplechuk, John I. Sewell
    Complex wave filters and wave group-delay equalisers in log-domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1996-1999 [Conf]
  500. Francisco Serra-Graells, Xavier Redondo
    1 V compact class-AB CMOS log filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2000-2003 [Conf]
  501. Tian-Bo Deng, Yong Lian
    Symmetry-based analytically closed-form design of variable fractional-delay FIR digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2004-2007 [Conf]
  502. Peyman Arian, Tapio Saramäki, Adly T. Fam
    A decomposition technique for cascaded IIR-like filter blocks generating linear-phase FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2008-2011 [Conf]
  503. Raija Lehto, Tapio Saramäki, Olli Vainio
    Synthesis of narrowband linear-phase FIR filters with a piecewise-polynomial impulse response. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2012-2015 [Conf]
  504. Jianghong Yu, Yong Lian
    Interpolation factor analysis for jointly optimized frequency-response masking filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2016-2019 [Conf]
  505. Yongtao Wang, Kaushik Roy
    A novel low-complexity method for parallel multiplierless implementation of digital FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2020-2023 [Conf]
  506. Yongzhi Liu, Zhiping Lin
    Design of complex FIR filters using the frequency-response masking approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2024-2027 [Conf]
  507. Wu-Sheng Lu, Takao Hinamoto
    A new minimax design for 2D FIR filters with low group delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2028-2031 [Conf]
  508. Arjuna Madanayake, Leonard T. Bruton
    A low-complexity scanned-array 3D IIR frequency-planar filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2032-2035 [Conf]
  509. Soo-Chang Pei, Meng-Ping Kao, Jian-Jiun Ding
    A perfect reconstruction filter bank with irrational down-sampling factors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2036-2039 [Conf]
  510. Krzysztof Galkowski, Anton Kummert
    Fractional polynomials and nD systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2040-2043 [Conf]
  511. Li Xu, Huijin Fan, Zhiping Lin, Yegui Xiao, Yoshihisa Anazawa
    A constructive procedure for multidimensional realization and LFR uncertainty modelling. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2044-2047 [Conf]
  512. Xiaomeng Wang, Weisi Lin, Ping Xue
    Demosaicing with improved edge direction detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2048-2051 [Conf]
  513. Ji Yao, Anthony J. Lawrance
    Approximate optimal demodulation for multi-user binary coherent chaos-shift-keying communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2052-2055 [Conf]
  514. Tohru A. Khan, Nobuoki Eshima, Yutaka Jitsumatsu, Tohru Kohda
    A novel code acquisition algorithm and its application to Markov spreading codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2056-2059 [Conf]
  515. Mingjian Liu, Hui Zhang, Ljiljana Trajkovic
    Stroboscopic model and bifurcations in TCP/RED. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2060-2063 [Conf]
  516. M. Naka, T. Saito, A. Tanaka
    An analog-to-digital converter with dynamic window for optimal rational number approximation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2064-2067 [Conf]
  517. Nikola Cackov, Zelimir Lucic, Momcilo Bogdanov, Ljiljana Trajkovic
    Wavelet-based estimation of long-range dependence in MPEG video traces. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2068-2071 [Conf]
  518. Yi Fan, Zhong-Ping Jiang, Shivendra S. Panwar, Hao Zhang
    Nonlinear output feedback control of TCP/AQM networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2072-2075 [Conf]
  519. Michael Dyer, David Taubman, Saeid Nooshabadi
    Reduced latency arithmetic decoder for JPEG2000 block decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2076-2079 [Conf]
  520. Shinya Kako, Kousuke Imamura, Hideo Hashimoto
    Matching pursuits using slant patterns and its dictionary design [video coding applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2080-2083 [Conf]
  521. Wei-Pin Lin, Chih-Ming Chen, Yung-Chang Chen
    Image compression with interpolation in wavelet-transform domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2084-2087 [Conf]
  522. Susanna Minasyan, Jaakko Astola, David Guevorkian
    An image compression scheme based on parametric Haar-like transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2088-2091 [Conf]
  523. Nantheera Anantrasirichai, Cedric Nishan Canagarajah, David R. Bull
    Lifting-based multi-view image coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2092-2095 [Conf]
  524. Ryusuke Miyamoto, Hiroaki Sugita, Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Yukihiro Nakamura
    High quality Motion JPEG2000 coding scheme based on the human visual system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2096-2099 [Conf]
  525. Hossein Zarei, Allan Ecker, Jinho Park, David J. Allstot
    A full-range all-pass variable phase shifter for multiple antenna receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2100-2103 [Conf]
  526. K. M. Naegle, Subhanshu Gupta, David J. Allstot
    Design considerations for a 10 GHz CMOS transmit-receive switch. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2104-2107 [Conf]
  527. Stefano Vitali, Eleonora Franchi, Antonio Gnudi
    A gain/phase mismatch calibration procedure for RF I/Q downconverters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2108-2111 [Conf]
  528. Farsheed Mahmoudi, C. Andre T. Salama
    8 GHz tunable CMOS quadrature generator using differential active inductors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2112-2115 [Conf]
  529. Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo
    A 5.25 GHz CMOS even harmonic mixer with an enhancing inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2116-2119 [Conf]
  530. Igor M. Filanovsky, Md. Mahbub Reja, Ahmed Allam
    A new CMOS wideband RF front-end for multistandard low-IF wireless receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2120-2123 [Conf]
  531. Jun-Yao Wang, Wen-Shyang Hwang, Wen-Fong Wang, Ce-Kuen Shieh
    An integrated rate control scheme for TCP-friendly MPEG-4 video transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2124-2127 [Conf]
  532. Chao-Hsuing Tseng, Hung-Ming Wang, Jar-Ferr Yang
    Improved and fast algorithms for intra 4×4 mode decision in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2128-2131 [Conf]
  533. Cheng-Nan Chiu, Chien-Tang Tseng, Chun-Jen Tsai
    Tightly-coupled MPEG-4 video encoder framework on asymmetric dual-core platforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2132-2135 [Conf]
  534. Wen-Nung Lie, Han-Ching Yeh, Tom C.-I. Lin, Chien-Fa Chen
    Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2136-2139 [Conf]
  535. Tsu-Ming Liu, Wen-Ping Lee, Ting-An Lin, Chen-Yi Lee
    A memory-efficient deblocking filter for H.264/AVC video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2140-2143 [Conf]
  536. Haiyan Shu, Lap-Pui Chau
    Variable frame rate transcoding considering motion information [video transcoding]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2144-2147 [Conf]
  537. Abhishek Bandyopadhyay, Guillermo J. Serrano, Paul E. Hasler
    Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2148-2151 [Conf]
  538. Pui-Tak So, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
    Ramp voltage supply using adiabatic charging principle. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2152-2155 [Conf]
  539. Esther Rodríguez-Villegas
    A 0.8 V, 360 nW Gm-C biquad based on FGMOS transistors [biquadratic filter]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2156-2159 [Conf]
  540. Esther Rodríguez-Villegas
    A 0.9 V offset compensated FGMOS comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2160-2163 [Conf]
  541. Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar
    Biasing techniques for subthreshold MOS resistive grids. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2164-2167 [Conf]
  542. Erhan Ozalevli, Paul E. Hasler
    Programmable floating-gate CMOS resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2168-2171 [Conf]
  543. David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler
    Indirect programming of floating-gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2172-2175 [Conf]
  544. Dan Stiurca
    A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13µ CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2176-2179 [Conf]
  545. Gunjan Mandal, Pradip Mandal
    Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2180-2183 [Conf]
  546. Tertulien Ndjountche, Fa-Long Luo, Christophe Bobda
    A CMOS front-end architecture for hard-disk drive read-channel equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2184-2187 [Conf]
  547. Peng Wang, Shiyuan Yang
    Soft fault test and diagnosis for analog circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2188-2191 [Conf]
  548. Hyung-Wook Jang, Sung-Sop Lee, Jin-Ku Kang
    A clock recovery circuit using half-rate 4×-oversampling PD. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2192-2195 [Conf]
  549. Alkis A. Hatzopoulos, Stelios Siskos, Charalambos A. Dimitriadis, Nikolaos P. Papadopoulos
    Built-in current sensor with reduced voltage drop using thin-film transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2196-2199 [Conf]
  550. Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan
    Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2200-2203 [Conf]
  551. Mimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel
    Digital built-in self-test of CMOS analog iterative decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2204-2207 [Conf]
  552. Dayu Yang, Foster F. Dai, Charles E. Stroud
    Built-in self-test for automatic analog frequency response measurement. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2208-2211 [Conf]
  553. Elena Dubrova
    Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2212-2215 [Conf]
  554. Nam-Po Chiang
    The chaotic numbers of the bipartite and tripartite graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2216-2218 [Conf]
  555. Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen
    Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2219-2222 [Conf]
  556. René Krenz
    Efficient computation of dominators in multiple-output circuit graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2223-2226 [Conf]
  557. Valentin Gies, Thierry M. Bernard, Alain Mérigot
    Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2227-2230 [Conf]
  558. Toshimasa Watanabe, Satoshi Taoka, Toshiya Mashima
    Maximum weight matching-based algorithms for k-edge-connectivity augmentation of a graph. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2231-2234 [Conf]
  559. Sabato Manfredi
    An AQM routing control for reducing congestion in communication networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2235-2238 [Conf]
  560. Jun Inagaki, Miki Haseyama
    GA-based applications for routing with an upper bound constraint. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2239-2242 [Conf]
  561. Paul V. Brennan, Dai Jiang, Jianxin Zhang
    Analyses of intermodulation effects in fractional-N frequency synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2243-2246 [Conf]
  562. Ewout Martens, Georges G. E. Gielen
    Behavioral modeling and simulation of weakly nonlinear sampled-data systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2247-2250 [Conf]
  563. Somnath Sengupta
    Analytical expression of HD3 due to non-linear MOS switch in MOSFET-C sample and hold circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2251-2254 [Conf]
  564. Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
    Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2255-2258 [Conf]
  565. Mohammed A. Hasan
    Root iterations and the computation of minimum and maximum zeros of polynomials. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2259-2262 [Conf]
  566. Hua Zhang, Dian Zhou, Yi Hu, Ruiming Li, Jianzhong Zhang
    Phase noise spectra analysis for LC oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2263-2266 [Conf]
  567. Guang Deng, Wai-Yin Ng
    A model-based approach for the development of LMS algorithms [adaptive filter applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2267-2270 [Conf]
  568. Yoshinori Ichikawa, Toshihiro Furukawa
    A new approach for non-uniform subband adaptive filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2271-2274 [Conf]
  569. Woon S. Gan, Kong A. Lee
    Adaptive filtering using constrained subband updates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2275-2278 [Conf]
  570. Heping Ding
    Performance of two novel fast affine projection adaptation algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2279-2282 [Conf]
  571. Felix Albu, Constantine Kotropoulos
    Coordinate descent iterations in pseudo affine projection algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2283-2286 [Conf]
  572. Aloys Mvuma, Shotaro Nishimura, Takao Hinamoto
    Adaptive IIR notch filters: state-space approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2287-2290 [Conf]
  573. S. Pal, D. J. Krusienski, W. Kenneth Jenkins
    Structured stochastic optimization strategies for problems with ill-conditioned error surfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2291-2294 [Conf]
  574. Dominic K. C. Ho, La-or Kovavisaruch
    Modified Taylor-series method for source and receiver localization using TDOA measurements with erroneous receiver positions. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2295-2298 [Conf]
  575. George E. Antoniou, Marinos T. Michael
    Generalized n-dimensional k-order systems: computing the transfer function. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2299-2302 [Conf]
  576. David B. H. Tay, Marimuthu Palaniswami
    Hilbert pair of wavelets via the matching design technique [matched filters]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2303-2306 [Conf]
  577. Charles W. Therrien
    The missing observations theorem and a new proof of Levinson's recursion. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2307-2308 [Conf]
  578. Lisandro Lovisolo, M. G. de Pinho, Eduardo A. B. da Silva, Paulo S. R. Diniz
    On the time-frequency content of Weyl-Heisenberg frames generated from odd and even functions [signal representation applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2309-2312 [Conf]
  579. Lahouari Ghouti, Ahmed Bouridane, Mohammad K. Ibrahim
    Image compression using texture modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2313-2316 [Conf]
  580. M. A. Hasan
    Unconstrained functional criteria for canonical correlation analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2317-2320 [Conf]
  581. Venkat Ramachandran, Majid Ahmadi, Christian S. Gargour
    Some properties of generalized 2-D mirror image and anti mirror image polynomials. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2321-2324 [Conf]
  582. Wang Sen, Cai Li
    Simulation of quantum cellular automaton circuits based on genetic simulated annealing algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2325-2328 [Conf]
  583. Paul Beckett, S. C. Goldstein
    Why area might reduce power in nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2329-2332 [Conf]
  584. Chien-Hsing Wu, Yan-Chr Tsai, Hwa-Long Tsai
    Quantum circuits for stabilizer codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2333-2336 [Conf]
  585. Sylvain Feruglio, Victor Fouad Hanna, Georges Alquié, Gabriel Vasilescu
    Exact noise analysis of a CMOS BDJ APS. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2337-2340 [Conf]
  586. Naokazu Muramatsu, Hiroshi Okazaki, Takao Waho
    A novel oscillation circuit using a resonant-tunneling diode. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2341-2344 [Conf]
  587. Paul Beckett
    Low-power spatial computing using dynamic threshold devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2345-2348 [Conf]
  588. Stefano Santi, Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti
    On the impact of traffic statistics on quality of service for networks on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2349-2352 [Conf]
  589. Daniel Andreasson, Shashi Kumar
    Slack-time aware routing in NoC systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2353-2356 [Conf]
  590. Kwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo
    An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2357-2360 [Conf]
  591. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    Self-calibrating networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2361-2364 [Conf]
  592. Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A novel approach for network on chip emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2365-2368 [Conf]
  593. Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
    A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2369-2372 [Conf]
  594. Jian-Hung Lin, Keshab K. Parhi
    VLSI architectures for stereoscopic video disparity matching and object extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2373-2376 [Conf]
  595. U. F. Siddiqi, Sadiq M. Sait, Aamir A. Farooqui
    Parallel algorithm for hardware implementation of inverse halftoning. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2377-2380 [Conf]
  596. Safar Hatami, Shervin Sharifi, Mahmoud Kamarei, Hossein Ahmadi
    Real-time image compression based on wavelet vector quantization, algorithm and VLSI architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2381-2384 [Conf]
  597. Mamun Bin Ibe Reaz, Faisal Mohd-Yasin, S. L. Tan, H. Y. Tan, Muhammad I. Ibrahimy
    Partial encryption of compressed images employing FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2385-2388 [Conf]
  598. Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata
    A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2389-2392 [Conf]
  599. Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu
    VLSI architecture design for a fast parallel label assignment in binary image. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2393-2396 [Conf]
  600. Bernhard Kuenzle, Leonard T. Bruton
    A novel low-complexity spatio-temporal ultra wide-angle polyphase cone filter bank applied to sub-pixel motion discrimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2397-2400 [Conf]
  601. Takao Hinamoto, Ken-ichi Iwata, Wu-Sheng Lu
    Minimization of L/sub 2/-sensitivity for a class of 2D state-space digital filters subject to L/sub 2/-scaling constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2401-2404 [Conf]
  602. Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy
    An efficient multidimensional decimation-in-frequency FHT algorithm based on the radix-2/4 approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2405-2408 [Conf]
  603. Hari C. Reddy, P. K. Rajan
    Generalized alpha-VSH polynomials and stability of delta-operator based 2D discrete-time systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2409-2412 [Conf]
  604. Isao Yamada
    High-resolution DOA estimation by algebraic phase unwrapping algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2413-2416 [Conf]
  605. Hyungju Park
    Optimal construction of compactly-supported multidimensional wavelets. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2417-2420 [Conf]
  606. Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
    Pre-capturing static pulsed flip-flops. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2421-2424 [Conf]
  607. Shahnam Khabiri, Maitham Shams
    A mathematical programming approach to designing MOS current-mode logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2425-2428 [Conf]
  608. Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo
    A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2429-2432 [Conf]
  609. Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen
    An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2433-2436 [Conf]
  610. Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli
    An approach to the design of PFSCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2437-2440 [Conf]
  611. Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler
    Programmable floating-gate techniques for CMOS inverters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2441-2444 [Conf]
  612. Min Pan, Chris C. N. Chu, J. Morris Chang
    Transition time bounded low-power clock tree construction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2445-2448 [Conf]
  613. Jingyu Xu, Xianlong Hong, Tong Jing
    Timing-driven global routing with efficient buffer insertion. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2449-2452 [Conf]
  614. Min Ma, Mourad Oulmane, Nicholas C. Rumin
    Explicit delay metric for interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2453-2456 [Conf]
  615. Satish K. Yanamanamanda, Jun Li, Janet Meiling Wang
    Uncertainty modeling of gate delay considering multiple input switching. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2457-2460 [Conf]
  616. Min Pan, Chris C. N. Chu, Hai Zhou
    Timing yield estimation using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2461-2464 [Conf]
  617. Kishore Kumar Muchherla, Pinhong Chen, Janet Meiling Wang
    A non-iterative equivalent waveform model for timing analysis in presence of crosstalk. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2465-2468 [Conf]
  618. Bin Zhou, Wing Hong Lau, Henry Shu-Hung Chung
    A theoretical solution for PWM with non-ideal transient response. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2469-2472 [Conf]
  619. Gerard Villar, Eduard Alarcón, Francesc Guinjoan, Alberto Poveda
    Efficiency-oriented switching frequency tuning for a buck switching power converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2473-2476 [Conf]
  620. Xiaoqun Wu, Chi Kong Tse, Octavian Dranga, Junan Lu
    Fast-scale instability of single-stage power-factor-correction power supplies. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2477-2480 [Conf]
  621. Yufei Zhou, Herbert H. C. Iu, Chi Kong Tse, Jun-Ning Chen
    Controlling chaos in DC/DC converters using optimal resonant parametric perturbation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2481-2484 [Conf]
  622. H. N. Nagaraja, Amit Patra, Debaprasad Kastha
    Generalized analysis of integrated magnetic component based low voltage interleaved DC-DC buck converter for efficiency improvement. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2485-2489 [Conf]
  623. K. C. Tam, Sin Chung Wong, Chi Kong Tse
    Wavelet-based piecewise approximation of steady-state waveforms for power electronics circuits [power converter examples]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2490-2493 [Conf]
  624. Behnam Sedighi, Behnam Analui, Mehrdad Sharif Bakhtiar
    A new architecture for analog sampled-data neural filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2494-2497 [Conf]
  625. Jin-Tsong Jeng, Chen-Chia Chuang
    Annealing robust Walsh function networks for modeling with outliers and digital implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2498-2501 [Conf]
  626. Hirotaka Inoue, Hiroyuki Narihisa
    Self-organizing neural grove: effective multiple classifier system with pruned self-generating neural trees. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2502-2505 [Conf]
  627. H. M. S. B. Senevirathna, Katsumi Yamashita, Hai Lin
    Self organizing map based channel prediction for OFDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2506-2509 [Conf]
  628. Nor H. Hamid, Alan F. Murray, David Laurenson, Scott Roy, Binjie Cheng
    Probabilistic computing with future deep sub-micrometer devices: a modelling approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2510-2513 [Conf]
  629. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
    Electrical and optical on-chip interconnects in scaled microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2514-2517 [Conf]
  630. Bharat B. Sukhwani, Janet Meiling Wang
    A stepwise constant conductance approach for simulating resonant tunneling diodes. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2518-2521 [Conf]
  631. Rumi Zhang, Wei Wang, Konrad Walus, Graham A. Jullien
    Performance comparison of quantum-dot cellular automata adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2522-2526 [Conf]
  632. Rui Tang, Fengming Zhang, Yong-Bin Kim
    QCA-based nano circuits design [adder design example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2527-2530 [Conf]
  633. Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang
    On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2531-2534 [Conf]
  634. Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici
    Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2535-2538 [Conf]
  635. Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
    A new technique for automatic error correction in Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2539-2542 [Conf]
  636. Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
    Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2543-2546 [Conf]
  637. Hashem Zare-Hoseini, Izzet Kale
    On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor Delta-Sigma modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2547-2550 [Conf]
  638. Andrea Xotta, Andrea Gerosa, Andrea Neviani
    A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLAN. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2551-2554 [Conf]
  639. Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo
    On reducing leakage quantization noise of multistage Sigma-Delta modulator using nonlinear oscillation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2555-2558 [Conf]
  640. Fa-Long Luo, Rolf Unbehauen, Tertulien Ndjountche
    Design of a high-frequency second-order Delta-Sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2559-2562 [Conf]
  641. Shouli Yan, Jingyu Hu, Tongyu Song
    Novel and robust constant-g/sub m/ technique for rail-to-rail CMOS amplifier input stages. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2563-2566 [Conf]
  642. Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio
    A constant-g/sub m/ rail-to-rail op amp input stage using dynamic current scaling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2567-2570 [Conf]
  643. Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio
    Constant-g/sub m/ techniques for rail-to-rail CMOS amplifier input stages: a comparative study. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2571-2574 [Conf]
  644. Feng Zhu, Shouli Yan, Jingyu Hu, Edgar Sánchez-Sinencio
    Feedforward reversed nested Miller compensation techniques for three-stage amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2575-2578 [Conf]
  645. Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
    Well-defined design procedure for a three-stage CMOS OTA. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2579-2582 [Conf]
  646. Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
    CMOS single-to-differential current amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2583-2586 [Conf]
  647. Zixue Zhao, Gang Li, Jiong Zhou
    Efficient digital filter structures with minimum roundoff noise gain. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2587-2590 [Conf]
  648. Tamal Bose, Zhongkai Zhang, O. Chauhan, Miloje S. Radenkovic
    Design of multiplier-free state-space digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2591-2594 [Conf]
  649. H. K. Kwan
    Multi-output passive digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2595-2598 [Conf]
  650. Mrinmoy Bhattacharya, Tapio Saramäki
    Fourth-order structures for multiplierless realizations of bandpass and bandstop digital filters transformed from all-pole lowpass filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2599-2602 [Conf]
  651. Jinn-Tsong Tsai, Jyh-Horng Chou, Tung-Kuan Liu, Chien-Han Chen
    Design of two-dimensional recursive filters by using a novel genetic algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2603-2606 [Conf]
  652. S. C. Chan, K. M. Tsui
    Wordlength determination algorithms for hardware implementation of linear time invariant systems with prescribed output accuracy. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2607-2610 [Conf]
  653. Mikko Valkama, Markku Renfors, Visa Koivunen
    Blind I/Q imbalance compensation in OFDM receivers based on adaptive I/Q signal decorrelation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2611-2614 [Conf]
  654. Yajun Kou, Wu-Sheng Lu, Andreas Antoniou
    Peak-to-average power-ratio reduction algorithms for OFDM systems via constellation extension. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2615-2618 [Conf]
  655. Wen-Rong Wu, Chao-Yuan Hsu
    Decision feedback IBI mitigation in OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2619-2622 [Conf]
  656. Hao Zhou, Yih-Fang Huang
    Fine timing synchronization using power delay profile for OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2623-2626 [Conf]
  657. Meng Wu, Wei-Ping Zhu
    A preamble-aided symbol and frequency synchronization scheme for OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2627-2630 [Conf]
  658. H. Cheng, Y. Zhou, S. C. Chan
    New approximate QR-LS algorithms for minimum output energy (MOE) receivers in DS-CDMA communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2631-2634 [Conf]
  659. Luís Bica Oliveira, Ahmed Allam, Igor M. Filanovsky, Jorge R. Fernandes
    On phase noise in quadrature cross-coupled oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2635-2638 [Conf]
  660. S. Raman, S. Krishnan, A. Fiedler
    A precise clock phase multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2639-2642 [Conf]
  661. Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chau-chin Su
    A spread spectrum clock generator for SATA-II. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2643-2646 [Conf]
  662. Maria J. Avedillo, José M. Quintana, José L. Huertas
    Robust frequency divider based on resonant tunneling devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2647-2650 [Conf]
  663. JunYoung Park, Michael P. Flynn
    Capacitively averaged multi-phase LC oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2651-2654 [Conf]
  664. Peter Singerl, Gernot Kubin
    Chebyshev approximation of baseband Volterra series for wideband RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2655-2658 [Conf]
  665. Tak-Song Chong, Oscar C. Au, Wing-San Chau, Tai-Wai Chan
    A partitioned linear minimum mean square estimator for error concealment [video decoder error concealment]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2659-2662 [Conf]
  666. Hsu-Feng Hsiao, Jenq-Neng Hwang
    The dynamics and stability of layered congestion control for multimedia streaming. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2663-2666 [Conf]
  667. Jian-Liang Lin, Soo-Chang Pei, Jenq-Neng Hwang
    Fine-grain layered multicast based on hierarchical bandwidth inference congestion control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2667-2670 [Conf]
  668. Tak-Piu Ip, Yui-Lam Chan, Chang-Hong Fu, Wan-Chi Siu
    Macroblock-based algorithm for dual-bitstream MPEG video streaming with VCR functionalities. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2671-2674 [Conf]
  669. Vincent Knopik, Didier Belot, B. Martineau
    20 dBm CMOS class AB power amplifier design for low cost 2 GHz-2.45 GHz consumer applications in a 0.13µm technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2675-2678 [Conf]
  670. F. Carrara, P. Filoramo, G. Bottiglieri, Giovanni Palmisano
    Silicon bipolar linear power amplifier for WCDMA mobile applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2679-2682 [Conf]
  671. Ellie Cijvat, Niklas Troedsson, Henrik Sjoland
    A 2.4 GHz CMOS power amplifier using internal frequency doubling. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2683-2686 [Conf]
  672. Kari Stadius, Kari Halonen
    Development of 4-GHz flip-chip VCO module. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2687-2690 [Conf]
  673. Ali Fard
    Phase noise and amplitude issues of a wide-band VCO utilizing a switched tuning resonator. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2691-2694 [Conf]
  674. Amin Q. Safarian, Payam Heydari
    A study of high-frequency regenerative frequency dividers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2695-2698 [Conf]
  675. Xu Huang, Allan C. Madoc, Andrew D. Cheetham
    Image multi-noise removal by wavelet-based Bayesian estimator. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2699-2702 [Conf]
  676. Bin B. Zhu, Shipeng Li, Min Feng 0002
    A framework of scalable layered access control for multimedia. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2703-2706 [Conf]
  677. Shuiming Ye, Qibin Sun, Ee-Chien Chang
    Error resilient content-based image authentication over wireless channel. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2707-2710 [Conf]
  678. Chen-Hsiu Huang, Chi-Hao Wu, Jin-Hau Kuo, Ja-Ling Wu
    A musical-driven video summarization system using content-aware mechanisms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2711-2714 [Conf]
  679. Woongki Baek, Jihong Kim
    Load-store reordering for low-power multimedia data transfers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2715-2718 [Conf]
  680. Dong Wang, Cedric Nishan Canagarajah, David R. Bull
    S frame design for multiple description video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2719-2722 [Conf]
  681. Alex Wong, Kong-Pang Pun, Yuan-Ting Zhang, Kevin Hung
    A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2723-2726 [Conf]
  682. Robert Rieger, Dipankar Pal, John Taylor, Peter Langlois
    Two preamplifiers for non-invasive on-chip recording of neural-signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2727-2730 [Conf]
  683. Meng-Lieh Sheu, Ta-Wei Lin, Wei-Hung Hsu
    Wide frequency range voltage controlled ring oscillators based on transmission gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2731-2734 [Conf]
  684. Mariko Ishihara, Yoshiaki Shirataki
    Applying multi-level sliced speech signals to bone-conducted communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2735-2738 [Conf]
  685. José António Beltran Gerald, Gonçalo Nuno Gomes Tavares, Moisés Simões Piedade, Elisio Gonçalves Varela, Ricardo Daniel Ribeiro
    RF-link for cortical neuroprosthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2739-2742 [Conf]
  686. Guoxing Wang, Wentai Liu, Mohanasankar Sivaprakasam, Mark S. Humayun, James D. Weiland
    Power supply topologies for biphasic stimulation in inductively powered implants. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2743-2746 [Conf]
  687. Denise M. Wilson, Andrew Moe, Brian Marquardt
    New architecture for miniaturized fluorescence analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2747-2750 [Conf]
  688. Mehdi Azadmehr, Jens Petter Abrahamsen, Philipp Häfliger
    A foveated AER imager chip [address event representation]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2751-2754 [Conf]
  689. Giorgio Gattiker, Karan V. I. S. Kaler, Martin P. Mintchev
    Microactuation of suspended MEMS beams. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2755-2758 [Conf]
  690. H. K. Kwan
    Three-layer symmetrical and asymmetrical associative memories for image applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2759-2762 [Conf]
  691. Favio Masson, Pedro Julián, Diego Puschini, P. Crocce, L. Arlenghi, Andreas G. Andreou, Pablo Sergio Mandolesi
    Hybrid sensor network and fusion algorithm for sound source localization. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2763-2766 [Conf]
  692. Vlatko Becanovic, Stefan Kubina, Alan A. Stocker
    An embedded vision system based on an analog VLSI vision sensor [robot vision applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2767-2770 [Conf]
  693. R. Takami, Kazuhiro Shimonomura, Seiji Kameda, Tetsuya Yagi
    An image pre-processing system employing neuromorphic 100×100 pixel silicon retina [robot vision applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2771-2774 [Conf]
  694. T. Zhou, T. B. Tarim
    An efficient and well-controlled IC system development flow: design approved specification and design guided test plan. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2775-2778 [Conf]
  695. Shujun Fu, Qiuqi Ruan, Wenqia Wang, Yu Li
    A compound anisotropic diffusion for ultrasonic image denoising and edge enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2779-2782 [Conf]
  696. Yan Sun, Jianming Lu, Akira Kobayashi, Takashi Yahagi
    Neural network ultrasonographic diagnosis system of cirrhosis using DWT for preprocessing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2783-2786 [Conf]
  697. Angela Hodge-Miller, Robert W. Newcomb
    System-on-a-chip (SoC) model of a micropump. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2787-2790 [Conf]
  698. Tony Pialis, Eric W. Hu, Khoman Phang
    A 1.8V low-jitter CMOS ring oscillator with supply regulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2791-2794 [Conf]
  699. Zhang-cai Huang, Atsushi Kurokawa, Yasuaki Inoue
    Effective capacitance for gate delay with RC loads. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2795-2798 [Conf]
  700. Chien-Hung Kuo, Yi-Shun Shih
    A frequency synthesizer using two different delay feedbacks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2799-2802 [Conf]
  701. Takashi Hisakado, Kohshi Okumura
    Moore test using Gray code. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2803-2806 [Conf]
  702. Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
    A low spur fractional-N frequency synthesizer architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2807-2810 [Conf]
  703. Shuenn-Yuh Lee, Chung-Han Cheng, Ming-Feng Huang, Shyh-Chyang Lee
    A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2811-2814 [Conf]
  704. Peter Wilson, Reuben Wilcock, Bashir M. Al-Hashimi
    A novel switched-current phase locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2815-2818 [Conf]
  705. Jonne Poikonen, Ari Paasio
    Rank identification for an analog ranked order filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2819-2822 [Conf]
  706. Guisheng Zhai, Bo Hu, Joe Imae, Tomoaki Kobayashi
    A unified procedure for locating the stabilizable regions of two-dimensional switched systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2823-2826 [Conf]
  707. Haipeng Ren, Chunfeng Jin, Tamotsu Ninomiya
    Low-frequency bifurcation behaviors of PFC converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2827-2830 [Conf]
  708. Masakazu Yagi, Takashi Hisakado, Kohshi Okumura
    Algebraic representation of error bounds for describing function using Groebner base [nonlinear circuit analysis example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2831-2834 [Conf]
  709. Abdelali El Aroudi, Luis Martinez-Salamero, Mohamed Orabi, Tamotsu Ninomiya
    Investigating stability and bifurcations of a boost PFC circuit under peak current mode control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2835-2838 [Conf]
  710. Takashi Yamamoto, Katsuki Amemiya, Takashi Yamaguchi
    Learning and recalling of phase pattern in coupled BVP oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2839-2842 [Conf]
  711. Tokunbo Ogunfunmi
    Realizing higher-order nonlinear Wiener adaptive systems [Wiener filter example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2843-2846 [Conf]
  712. Yusuke Hioka, Nozomu Hamada
    Speaker direction tracking using microphones located at the vertices of equilateral-triangle. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2847-2850 [Conf]
  713. Chun-Nan Liu, Tsung-Han Tsai
    SoC platform based design of MPEG-2/4 AAC audio decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2851-2854 [Conf]
  714. M. Shahidur Rahman, Tetsuya Shimamura
    Linear prediction using homomorphic deconvolution in the autocorrelation domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2855-2858 [Conf]
  715. Jen-Feng Chung, Der-Jenq Liu, Chin-Teng Lin
    Multiband room effect simulator for 5.1-channel sound system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2859-2862 [Conf]
  716. Farook Sattar, Moe Pwint
    A new speech/non-speech classification method using minimal Walsh basis functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2863-2866 [Conf]
  717. Henrik Svensson, Viktor Öwall, Krzysztof Kuchcinski
    Implementation aspects of a novel speech packet loss concealment method. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2867-2870 [Conf]
  718. Dimitrios Ververidis, Constantine Kotropoulos
    Emotional speech classification using Gaussian mixture models. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2871-2874 [Conf]
  719. Siow Yong Low, Sven Nordholm
    A robust multichannel speech enhancement method based on decorrelation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2875-2878 [Conf]
  720. Hsien-Huang Wu, Ming-Hwa Sheu, Tung-Yu Yang
    Directional interpolation for field-sequential stereoscopic video. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2879-2882 [Conf]
  721. Shih-Yu Huang, Chun-Ming Huang
    An efficient block motion estimation algorithm on multimedia processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2883-2886 [Conf]
  722. He Wei-feng, Bi Yun-long, Mao Zhi-gang
    Efficient frame-level pipelined array architecture for full-search block-matching motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2887-2890 [Conf]
  723. Seiichiro Hiratsuka, Satoshi Goto, Takaaki Baba, Takeshi Ikenaga
    A locally adaptive subsampling algorithm for software based motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2891-2894 [Conf]
  724. Ming-Chieh Chi, Mei-Juan Chen, Jia-Hwa Liu, Ching-Ting Hsu
    High performance error concealment algorithm by motion vector refinement for MPEG-4 video. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2895-2898 [Conf]
  725. Yan Zhao, Dong Tian, M. M. Hannukasela, Moncef Gabbouj
    Spatial error concealment based on directional decision and intra prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2899-2902 [Conf]
  726. Hoi-Kok Cheung, Wan-Chi Siu, David Dagan Feng
    New block-based motion estimation for sequences with illumination variation and its application to video mosaicking. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2903-2906 [Conf]
  727. Yueh-Yi Wang, Chun-Jen Tsai
    An efficient dual-interpolator architecture for sub-pixel motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2907-2910 [Conf]
  728. Nicolò Manaresi, Gianni Medoro, Aldo Romani, Marco Tartagni, Roberto Guerrieri
    Beyond the microscope: embedded detectors for cell biology applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2911-2914 [Conf]
  729. Alexander Frey, Meinrad Schienle, Christian Paulus, Z. Jun, Franz Hofmann, Petra Schindler-Bauer, Birgit Holzapfl, Melanie Atzesberger, Gottfried Beer, Michaela Fritz, Thomas Haneder, Hans-Christian Hanke, Roland Thewes
    A digital CMOS DNA chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2915-2918 [Conf]
  730. Ian Theodore Young, Ventzeslav P. Iordanov, Heidi R. C. Dietrich, Andre Bossche
    Nanoliter array advances: miniaturized, high-speed PCR sensing & control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2919-2922 [Conf]
  731. Jun Ohta, Keiichiro Kagawa, Takashi Tokuda, Masahiro Nunoshita
    Retinal prosthesis device based on pulse-frequency-modulation vision chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2923-2926 [Conf]
  732. Wentai Liu, W. Fink, M. Tarbell, Mohanasankar Sivaprakasam
    Image processing and interface for retinal visual prostheses. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2927-2930 [Conf]
  733. To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
    Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2931-2934 [Conf]
  734. Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rainer Dorsch, Hans-Joachim Wunderlich
    Development of an audio player as system-on-a-chip using an open source platform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2935-2938 [Conf]
  735. Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari
    Mapping system-on-chip designs from 2-D to 3-D ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2939-2942 [Conf]
  736. Aleksandar Beric, Gerard de Haan, Jef L. van Meerbergen, Ramanathan Sethuraman
    Algorithm/architecture co-design of the generalized sampling theorem based de-interlacer [video signal processing]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2943-2946 [Conf]
  737. Suk Hyun Yoon, Jong Ha Moon, Myung Hoon Sunwoo
    Efficient DSP architecture for high-quality audio algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2947-2950 [Conf]
  738. Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen, Jeffrey T. Draper
    An area-efficient and protected network interface for processing-in-memory systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2951-2954 [Conf]
  739. Inwhee Joe
    Optimal packet length with energy efficiency for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2955-2957 [Conf]
  740. K. Mase, S. Kameyama
    Multihop hello guided routing-reactive for mobile ad hoc networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2958-2961 [Conf]
  741. Keisuke Nakano, Rajesh Krishna Panta, Masakazu Sengoku, Shoji Shinoda
    On performance of a charging/rewarding scheme in mobile ad-hoc networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2962-2966 [Conf]
  742. Naoyoshi Murakami, Tomoyuki Ohta, Yoshiaki Kakuda
    Effective division and merger of the autonomous clustering scheme for highly mobile large ad hoc networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2967-2970 [Conf]
  743. Thomas H. Clausen, Emmanuel Baccelli
    A simple address autoconfiguration mechanism for OLSR [MANET routing protocol]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2971-2974 [Conf]
  744. Changsu Suh, Young-Bae Ko
    A traffic aware, energy efficient MAC protocol for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2975-2978 [Conf]
  745. Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu
    A novel reseeding mechanism for pseudo-random testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2979-2982 [Conf]
  746. Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong
    An embedded processor based SOC test platform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2983-2986 [Conf]
  747. T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu
    On the fault diagnosis in the presence of unknown fault models using pass/fail information. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2987-2990 [Conf]
  748. Ghazanfar Asadi, Mehdi Baradaran Tahoori
    An analytical approach for soft error rate estimation in digital circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2991-2994 [Conf]
  749. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    Electric field for detecting open leads in CMOS logic circuits by supply current testing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2995-2998 [Conf]
  750. Di Long, Xianlong Hong, Sheqin Dong
    Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2999-3002 [Conf]
  751. Hao-Sheng Hou, Shoou-Jinn Chang, Yan-Kuin Su
    Economical passive filter synthesis using genetic programming based on tree representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:3003-3006 [Conf]
  752. Devrim Yilmaz Aksin, Franco Maloberti
    Symbolic small-signal analysis (SSA) tool. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:3007-3010 [Conf]
  753. M. A. Selim, Aly E. Salama
    Accurate high frequency noise modeling in SiGe HBTs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:3011-3014 [Conf]
  754. Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
    Modeling of substrate noise block properties for early prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:3015-3018 [Conf]

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  756. A novel post-nonlinear ICA-based reflectance model for 3D surface reconstruction. [Citation Graph (, )][DBLP]


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  758. Robust super-exponential methods for blind equalization of SISO systems with additive Gaussian noise. [Citation Graph (, )][DBLP]


  759. Necessary and sufficient conditions for LTI systems to preserve signal richness. [Citation Graph (, )][DBLP]


  760. A fuzzy algorithm for navigation of mobile robots in unknown environments. [Citation Graph (, )][DBLP]


  761. FPGA implementation of a recurrent neural fuzzy network for on-line temperature control. [Citation Graph (, )][DBLP]


  762. LMI-based neurocontroller for guaranteed cost control of uncertain time-delay systems. [Citation Graph (, )][DBLP]


  763. The use of NNs in MRAC to control nonlinear magnetic levitation system. [Citation Graph (, )][DBLP]


  764. BMI-based neurocontroller for state-feedback guaranteed cost control of discrete-time uncertain system. [Citation Graph (, )][DBLP]


  765. Architecture design of the re-configurable 2-D von Neumann cellular automata for image encryption application. [Citation Graph (, )][DBLP]


  766. Super-stable energy based switching control scheme for DC-DC buck converter circuits. [Citation Graph (, )][DBLP]


  767. Sliding-mode control design of parallel-connected switching converters for modular transformerless DC-AC step-up conversion. [Citation Graph (, )][DBLP]


  768. Integrated charge-control single-inductor dual-output step-up/step-down converter. [Citation Graph (, )][DBLP]


  769. Predictive valley current controller for two inductor buck converter. [Citation Graph (, )][DBLP]


  770. Boundary control of a bipolar square-wave generator using second-order switching surface. [Citation Graph (, )][DBLP]


  771. A pseudo-CCM buck converter with freewheel switching control. [Citation Graph (, )][DBLP]


  772. A cascade 3-1-1 multibit /spl Sigma//spl Delta/ A/D modulator with reduced sensitivity to non-idealities. [Citation Graph (, )][DBLP]


  773. A digital background calibration method for mash /spl Sigma/-/spl Delta/ modulators by using coefficient estimation. [Citation Graph (, )][DBLP]


  774. A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. [Citation Graph (, )][DBLP]


  775. A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. [Citation Graph (, )][DBLP]


  776. Analysis of clock jitter error in multibit continuous-time /spl Sigma//spl Delta/ modulators with NRZ feedback waveform. [Citation Graph (, )][DBLP]


  777. A low-power /spl Delta//spl Sigma/ modulator with low capacitor spread for multi-standard receiver applications. [Citation Graph (, )][DBLP]


  778. A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal. [Citation Graph (, )][DBLP]


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  780. Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). [Citation Graph (, )][DBLP]


  781. Switched-capacitor circuits using a single-phase scheme. [Citation Graph (, )][DBLP]


  782. An approach to an efficient reduction of the switching noise in switched-current circuits. [Citation Graph (, )][DBLP]


  783. A low-voltage low-distortion MOS sampling switch. [Citation Graph (, )][DBLP]


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  785. Application of radiation mode in desired sound field generation using loudspeaker array. [Citation Graph (, )][DBLP]


  786. A robust pitch estimation approach for colored noise-corrupted speech. [Citation Graph (, )][DBLP]


  787. Noisy autoregressive system identification by the ramp cepstrum of one-sided autocorrelation function. [Citation Graph (, )][DBLP]


  788. Artificial bandwidth extension of telephony speech by data hiding. [Citation Graph (, )][DBLP]


  789. Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors. [Citation Graph (, )][DBLP]


  790. Spectral correlation MUSIC algorithm for cyclostationary signals by exploitation of new array configuration. [Citation Graph (, )][DBLP]


  791. A frequency-domain SIR maximizing time-domain equalizer for VDSL systems. [Citation Graph (, )][DBLP]


  792. Low-power log-MAP turbo decoding based on reduced metric memory access. [Citation Graph (, )][DBLP]


  793. A design of orthogonal interleavers for multimodes turbo en-decoders. [Citation Graph (, )][DBLP]


  794. Efficient per-carrier channel equalizer for filter bank based multicarrier systems. [Citation Graph (, )][DBLP]


  795. Robustness analysis of a decision feedback generalized sidelobe canceller. [Citation Graph (, )][DBLP]


  796. Stability analysis for switched systems with continuous-time and discrete-time subsystems: a Lie algebraic approach. [Citation Graph (, )][DBLP]


  797. Stability analysis of pulse-width-modulated feedback systems with type 2 modulation: the critical case. [Citation Graph (, )][DBLP]


  798. Robust stabilization of control systems using piecewise linear Lyapunov functions and evolutionary algorithm. [Citation Graph (, )][DBLP]


  799. Observer synthesis for Lipschitz discrete-time systems. [Citation Graph (, )][DBLP]


  800. Stick-slip oscillations in resonant power converters. [Citation Graph (, )][DBLP]


  801. Double-bounded homotopy for analysing nonlinear resistive circuits. [Citation Graph (, )][DBLP]


  802. A framework for real time gesture recognition for interactive mobile robots. [Citation Graph (, )][DBLP]


  803. A method of 3D face recognition based on principal component analysis algorithm. [Citation Graph (, )][DBLP]


  804. Object tracking in video pictures based on image segmentation and pattern matching. [Citation Graph (, )][DBLP]


  805. Automatic video region-of-interest determination based on user attention model. [Citation Graph (, )][DBLP]


  806. Video segmentation using multiscale feature extraction and fusion. [Citation Graph (, )][DBLP]


  807. A 24 GHz dual-modulus prescaler in 90nm CMOS. [Citation Graph (, )][DBLP]


  808. A new technique for design CMOS LNA for multi-standard receivers. [Citation Graph (, )][DBLP]


  809. An AC-coupled direct-conversion receiver for Global Positioning System. [Citation Graph (, )][DBLP]


  810. Design methodology for the optimization of transformer-loaded RF circuits. [Citation Graph (, )][DBLP]


  811. An 18 GHz low noise high linearity active mixer in SiGe. [Citation Graph (, )][DBLP]


  812. Variable-gain up-converter with current reuse for WCDMA wireless transmitters. [Citation Graph (, )][DBLP]


  813. An effective algorithm for delay constrained least cost unicast routing. [Citation Graph (, )][DBLP]


  814. Seamless roaming in wireless networks for video streaming. [Citation Graph (, )][DBLP]


  815. Packet scheduling based on GeoY/G/infinity input process modeling for streaming video. [Citation Graph (, )][DBLP]


  816. A robust H.264 video streaming scheme for portable devices. [Citation Graph (, )][DBLP]


  817. A novel adaptive video playout control for video streaming over mobile cellular environment. [Citation Graph (, )][DBLP]


  818. Rate-distortion optimized video streaming with smooth quality constraint. [Citation Graph (, )][DBLP]


  819. High-order linear transformation MOSFET-C filters using operational transresistance amplifiers. [Citation Graph (, )][DBLP]


  820. Active RC filter with reduced capacitance by current division technique. [Citation Graph (, )][DBLP]


  821. Time-domain symmetry as criterion for band-pass equalizer design. [Citation Graph (, )][DBLP]


  822. Analog complex wavelet filters. [Citation Graph (, )][DBLP]


  823. Output noise of generalized high-order allpole OTA-C filters. [Citation Graph (, )][DBLP]


  824. 10-th order programmable low-pass CMOS integrated pulse-shaping filter. [Citation Graph (, )][DBLP]


  825. An insensitive current mode universal biquad: multi-input multi-output. [Citation Graph (, )][DBLP]


  826. Low-sensitivity current-mode active-RC filters using impedance tapering. [Citation Graph (, )][DBLP]


  827. VLSI implementation of type-2 fuzzy inference processor. [Citation Graph (, )][DBLP]


  828. A power-driven multiplication instruction-set design method for ASIPs. [Citation Graph (, )][DBLP]


  829. A CORDIC processor with efficient table-lookup schemes for rotations and on-line scale factor compensations. [Citation Graph (, )][DBLP]


  830. Elimination of sign precomputation in flat CORDIC. [Citation Graph (, )][DBLP]


  831. Novel instructions and their hardware architecture for video signal processing. [Citation Graph (, )][DBLP]


  832. A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing. [Citation Graph (, )][DBLP]


  833. Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems. [Citation Graph (, )][DBLP]


  834. Implementation of a cycle by cycle variable speed processor. [Citation Graph (, )][DBLP]


  835. A hardware-based longest prefix matching scheme for TCAMs. [Citation Graph (, )][DBLP]


  836. A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. [Citation Graph (, )][DBLP]


  837. A modified spiral search motion estimation algorithm and its embedded system implementation. [Citation Graph (, )][DBLP]


  838. HIBI-based multiprocessor SoC on FPGA. [Citation Graph (, )][DBLP]


  839. Dual use of power lines for data communications in a system-on-chip environment. [Citation Graph (, )][DBLP]


  840. A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. [Citation Graph (, )][DBLP]


  841. A 64-MHz/spl sim/1920-MHz programmable spread-spectrum clock generator. [Citation Graph (, )][DBLP]


  842. Reduction in spectral peaks of DC-DC converters using chaos-modulated clock. [Citation Graph (, )][DBLP]


  843. Nonlinear echo cancellation using an expanded correlation LMS algorithm. [Citation Graph (, )][DBLP]


  844. A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis. [Citation Graph (, )][DBLP]


  845. Dynamics in a controlled flow model of a switching system. [Citation Graph (, )][DBLP]


  846. A performance estimation method for chaotic spread spectrum clock processes. [Citation Graph (, )][DBLP]


  847. Chaotification of nonlinear systems described by the fuzzy hyperbolic model. [Citation Graph (, )][DBLP]


  848. Experimental verification of 3-D hysteresis multi-scroll chaotic attractors. [Citation Graph (, )][DBLP]


  849. Cascading failures in scale-free coupled map lattices. [Citation Graph (, )][DBLP]


  850. Bifurcation and transitional dynamics in three-coupled oscillators with hard type nonlinearity. [Citation Graph (, )][DBLP]


  851. Bifurcation analysis of a circuit-related piecewise-affine map. [Citation Graph (, )][DBLP]


  852. On rigorous study of Poincare maps defined by piecewise linear systems [electronic circuit example]. [Citation Graph (, )][DBLP]


  853. A piecewise constant switched chaotic circuit with rect-rippling return maps. [Citation Graph (, )][DBLP]


  854. Observer-based approach for synchronization of a time-delayed, Chua's circuit. [Citation Graph (, )][DBLP]


  855. A fast bitplane combination algorithm for bitplane coded scalable image/video. [Citation Graph (, )][DBLP]


  856. Optimized decoding scheme for erroneous MPEG-4 FGS bitstream. [Citation Graph (, )][DBLP]


  857. A novel algorithm of spatial scalability for scrambled video. [Citation Graph (, )][DBLP]


  858. A low complexity architecture for binary image erosion and dilation using structuring element decomposition. [Citation Graph (, )][DBLP]


  859. Am object-based approach to plenoptic videos. [Citation Graph (, )][DBLP]


  860. Parameters estimation applied to automatic video processing algorithms validation. [Citation Graph (, )][DBLP]


  861. Fast pixel-based video scene change detection. [Citation Graph (, )][DBLP]


  862. Robust group-of-picture architecture for video transmission over error-prone channels. [Citation Graph (, )][DBLP]


  863. A novel interleaving algorithm for robust video transmission. [Citation Graph (, )][DBLP]


  864. A fast global motion estimation for moving objects segmentation using moment-preserving technique. [Citation Graph (, )][DBLP]


  865. Shot change detection on H.264/AVC compressed video. [Citation Graph (, )][DBLP]


  866. Algorithmic optimization of H.264/AVC encoder. [Citation Graph (, )][DBLP]


  867. Low complexity RDO mode decision based on a fast coding-bits estimation model for H.264/AVC. [Citation Graph (, )][DBLP]


  868. Viewpoint switching in multiview video streaming. [Citation Graph (, )][DBLP]


  869. A flexible macroblock ordering with 3D MBAMAP for H.264/AVC. [Citation Graph (, )][DBLP]


  870. CMOS sensor array for electrical imaging of neuronal activity. [Citation Graph (, )][DBLP]


  871. Integrated optical computing: system-on-chip for surface plasmon resonance imaging. [Citation Graph (, )][DBLP]


  872. Pulse modulation CMOS image sensor for bio-fluorescence imaging applications. [Citation Graph (, )][DBLP]


  873. CMOS contact imager for monitoring cultured cells. [Citation Graph (, )][DBLP]


  874. A CMOS capacitance sensor for cell adhesion characterization. [Citation Graph (, )][DBLP]


  875. Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. [Citation Graph (, )][DBLP]


  876. Hierarchical instruction encoding for VLIW digital signal processors. [Citation Graph (, )][DBLP]


  877. Design of superscalar processor with multi-bank register file. [Citation Graph (, )][DBLP]


  878. Dynamic coarse grain dataflow reconfiguration technique for real-time systems design. [Citation Graph (, )][DBLP]


  879. Application specific instruction-set processor generation for video processing based on loop optimization. [Citation Graph (, )][DBLP]


  880. An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays. [Citation Graph (, )][DBLP]


  881. Fast 802.11 link adaptation for real-time video streaming by cross-layer signaling. [Citation Graph (, )][DBLP]


  882. A study of encoding and decoding techniques for syndrome-based video coding. [Citation Graph (, )][DBLP]


  883. Congestion-optimized scheduling of video over wireless ad hoc networks. [Citation Graph (, )][DBLP]


  884. A fast greedy algorithm for routing concurrent video flows. [Citation Graph (, )][DBLP]


  885. Image transmission over IEEE 802.15.4 and ZigBee networks. [Citation Graph (, )][DBLP]


  886. Integrated multi-objective cross-layer optimization for wireless multimedia transmission. [Citation Graph (, )][DBLP]


  887. A countermeasure against differential power analysis based on random delay insertion. [Citation Graph (, )][DBLP]


  888. Litho-driven layouts for reducing performance variability. [Citation Graph (, )][DBLP]


  889. Automatic monitor generation from regular expression based specifications for module interface verification. [Citation Graph (, )][DBLP]


  890. Power and delay analysis of 4: 2 compressor cells. [Citation Graph (, )][DBLP]


  891. Timing error correction techniques for voltage-scalable on-chip memories. [Citation Graph (, )][DBLP]


  892. Incremental timing optimization for automatic layout generation. [Citation Graph (, )][DBLP]


  893. An FPGA based implementation of G.729. [Citation Graph (, )][DBLP]


  894. Fast estimation of area-delay trade-offs in circuit sizing. [Citation Graph (, )][DBLP]


  895. Performance analysis by topology indexed lookup tables. [Citation Graph (, )][DBLP]


  896. Optimized design of source coupled logic gates in GaAs HEMT technology. [Citation Graph (, )][DBLP]


  897. Initial solution for the optimum design delay equalizers. [Citation Graph (, )][DBLP]


  898. A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. [Citation Graph (, )][DBLP]


  899. F-SEONS: a second-order frequency-domain algorithm for noisy convolutive source separation. [Citation Graph (, )][DBLP]


  900. A class of novel blind source extraction algorithms based on a linear predictor. [Citation Graph (, )][DBLP]


  901. New Riemannian metrics for improvement of convergence speed in ICA based learning algorithms. [Citation Graph (, )][DBLP]


  902. A class of space-time code for blind detection. [Citation Graph (, )][DBLP]


  903. Blind IQ error compensation in a direct conversion receiver for DVB-T. [Citation Graph (, )][DBLP]


  904. Recursive semi-blind decoding of a space-time block code over frequency-selective channel. [Citation Graph (, )][DBLP]


  905. Identification of road signs using a new ridgelet network. [Citation Graph (, )][DBLP]


  906. Hardware friendly vector quantization algorithm. [Citation Graph (, )][DBLP]


  907. A compact distance cell for analog classifiers. [Citation Graph (, )][DBLP]


  908. A learning algorithm for enhancing the generalization ability of support vector machines. [Citation Graph (, )][DBLP]


  909. Two-level decoupled Hamming network for associative memory under noisy environment. [Citation Graph (, )][DBLP]


  910. Pulse width modulator using a phase-locked loop variable phase shifter. [Citation Graph (, )][DBLP]


  911. Three-phase power factor corrector based on capacitor-clamped topology. [Citation Graph (, )][DBLP]


  912. Three-phase active power filter under unbalanced condition. [Citation Graph (, )][DBLP]


  913. A 36-V H-bridge driver interface in a standard 0.35-/spl mu/m CMOS process. [Citation Graph (, )][DBLP]


  914. Design of class E backlight module incorporating piezoelectric transformer. [Citation Graph (, )][DBLP]


  915. An integrated electronic ballast for small wattage high intensity discharge lamps. [Citation Graph (, )][DBLP]


  916. A 2-path bandpass sigma-delta modulator utilizing a 3-path structure. [Citation Graph (, )][DBLP]


  917. Digitally tuned bandpass sigma delta modulator for wireless communications. [Citation Graph (, )][DBLP]


  918. Design of continuous-time /spl Sigma//spl Delta/ modulators with sine-shaped feedback DACs. [Citation Graph (, )][DBLP]


  919. A tunable bandpass /spl Delta//spl Sigma/ modulator using double sampling. [Citation Graph (, )][DBLP]


  920. DAC compensation for continuous-time delta-sigma modulators. [Citation Graph (, )][DBLP]


  921. A 0.8V Delta-Sigma modulator using DTMOS technique. [Citation Graph (, )][DBLP]


  922. Performance analysis of high-speed MOS transistors with different layout styles. [Citation Graph (, )][DBLP]


  923. An optimization technique for RF buffers with active inductors. [Citation Graph (, )][DBLP]


  924. Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator. [Citation Graph (, )][DBLP]


  925. Calculation of intermodulation distortion in CMOS transconductance stage. [Citation Graph (, )][DBLP]


  926. A novel 1.5V DC offset cancellation CMOS down conversion mixer. [Citation Graph (, )][DBLP]


  927. Low voltage analog synthesizer of orthogonal signals: a current-mode approach. [Citation Graph (, )][DBLP]


  928. Improved design of fractional order differentiator using fractional sample delay. [Citation Graph (, )][DBLP]


  929. Digital differentiator design using fractional sample delay filter. [Citation Graph (, )][DBLP]


  930. Digital differentiators for narrow band applications in the lower to midband range. [Citation Graph (, )][DBLP]


  931. Variable multi-output passive digital filters. [Citation Graph (, )][DBLP]


  932. High tuning accuracy design of variable IIR filters as a cascade of identical sub-filters. [Citation Graph (, )][DBLP]


  933. A new cascaded modified CIC-cosine decimation filter. [Citation Graph (, )][DBLP]


  934. Correlation-based adaptive filters for channel identification. [Citation Graph (, )][DBLP]


  935. Generalized sidelobe cancellers with leakage constraints. [Citation Graph (, )][DBLP]


  936. Generalized partially adaptive concentric ring array. [Citation Graph (, )][DBLP]


  937. A subspace constrained constant modulus algorithm for blind array. [Citation Graph (, )][DBLP]


  938. A high-throughput DLMS adaptive algorithm. [Citation Graph (, )][DBLP]


  939. Canards in a slow-fast continuous piecewise linear vector field. [Citation Graph (, )][DBLP]


  940. Path following circuits - SPICE-oriented numerical methods where formulas are described by circuits $. [Citation Graph (, )][DBLP]


  941. Analysis of a hysteretic oscillator through a mixed time-frequency domain approach. [Citation Graph (, )][DBLP]


  942. On the identifiability of bilinear systems. [Citation Graph (, )][DBLP]


  943. Effects of variations of load distribution on network performance. [Citation Graph (, )][DBLP]


  944. On passivity enforcement for macromodels of S-parameter based tabulated subnetworks. [Citation Graph (, )][DBLP]


  945. Compressed-domain fall incident detection for intelligent home surveillance. [Citation Graph (, )][DBLP]


  946. Non-linear learning factor control for statistical adaptive background subtraction algorithm. [Citation Graph (, )][DBLP]


  947. An automated volumetric segmentation system combining multiscale and statistical reasoning. [Citation Graph (, )][DBLP]


  948. Perceived visual quality metric based on error spread and contrast. [Citation Graph (, )][DBLP]


  949. A unified probabilistic approach to face detection and tracking. [Citation Graph (, )][DBLP]


  950. A novel automatic white balance method for digital still cameras. [Citation Graph (, )][DBLP]


  951. Computationally efficient DOA estimation in a multipath environment using covariance differencing and iterative spatial smoothing. [Citation Graph (, )][DBLP]


  952. A test strategy for time-to-digital converters using dynamic element matching and dithering. [Citation Graph (, )][DBLP]


  953. A complete receiver solution for a chaotic direct-sequence spread spectrum communication system. [Citation Graph (, )][DBLP]


  954. A new method of an IF I/Q demodulator for narrowband signals. [Citation Graph (, )][DBLP]


  955. Experimental gigabit multidrop serial backplane for high speed digital systems. [Citation Graph (, )][DBLP]


  956. ASIC design of fast IP-lookup for next generation IP router. [Citation Graph (, )][DBLP]


  957. Baseball event detection using game-specific feature sets and rules. [Citation Graph (, )][DBLP]


  958. Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition. [Citation Graph (, )][DBLP]


  959. Effective shot boundary classification using video spatial-temporal information. [Citation Graph (, )][DBLP]


  960. An efficient method for face recognition under varying illumination. [Citation Graph (, )][DBLP]


  961. Event detection using multimodal feature analysis. [Citation Graph (, )][DBLP]


  962. Video shot segmentation using fusion of SVD and mutual information features. [Citation Graph (, )][DBLP]


  963. A CMOS bandgap voltage reference with absolute value and temperature drift trims. [Citation Graph (, )][DBLP]


  964. A very low drop voltage regulator using an NMOS output transistor. [Citation Graph (, )][DBLP]


  965. New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation. [Citation Graph (, )][DBLP]


  966. A single circuit solution for voltage sensors. [Citation Graph (, )][DBLP]


  967. Design considerations in bandgap references over process variations. [Citation Graph (, )][DBLP]


  968. A low-power digital PWM DC/DC converter based on passive sigma-delta modulator. [Citation Graph (, )][DBLP]


  969. A low voltage low 1/f noise CMOS bandgap reference. [Citation Graph (, )][DBLP]


  970. Observability analysis by measurement Jacobian matrix for state estimation. [Citation Graph (, )][DBLP]


  971. Recognition of power quality events using wavelet-based dynamic structural neural networks. [Citation Graph (, )][DBLP]


  972. Real-time phasor measurement for low frequency oscillation in power system. [Citation Graph (, )][DBLP]


  973. Evaluating performance of hybrid-type power system simulator based on transient stability analysis: a dynamical system approach. [Citation Graph (, )][DBLP]


  974. Fault location in automated distribution network. [Citation Graph (, )][DBLP]


  975. Signal waveform monitoring for power systems. [Citation Graph (, )][DBLP]


  976. On-line learning applied to power system transient stability prediction. [Citation Graph (, )][DBLP]


  977. A study on an ASIC design technique for digital protective relays. [Citation Graph (, )][DBLP]


  978. DBNS addition using cellular neural networks. [Citation Graph (, )][DBLP]


  979. Analog networks for mixed domain spatiotemporal filtering. [Citation Graph (, )][DBLP]


  980. A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing. [Citation Graph (, )][DBLP]


  981. Selective similarity function for VLSI analog signal processing. [Citation Graph (, )][DBLP]


  982. A Gray-coded digital-to-analog converter for a mixed-mode processor array. [Citation Graph (, )][DBLP]


  983. Fixed-current method for programming large floating-gate arrays. [Citation Graph (, )][DBLP]


  984. Template design for binary-programmable cellular nonlinear networks. [Citation Graph (, )][DBLP]


  985. A complex texture classification algorithm based on Gabor-type filtering cellular neural networks and self-organized fuzzy inference neural networks. [Citation Graph (, )][DBLP]


  986. A beamforming method in UWB pulse array based on neural network. [Citation Graph (, )][DBLP]


  987. The modem for ultra-wideband communication employing surface-acoustic-wave devices. [Citation Graph (, )][DBLP]


  988. Using CLNS for FFTs in OFDM demodulation of UWB receivers. [Citation Graph (, )][DBLP]


  989. Dual drain-line distributed cell design for multi-Gbit/s transversal filter implementations. [Citation Graph (, )][DBLP]


  990. A systematic approach to CMOS low noise amplifier design for ultrawideband applications. [Citation Graph (, )][DBLP]


  991. Simple polar-loop transmitter for dual-mode Bluetooth. [Citation Graph (, )][DBLP]


  992. Functional modeling techniques for a wireless LAN OFDM transceiver. [Citation Graph (, )][DBLP]


  993. A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications. [Citation Graph (, )][DBLP]


  994. Transaction level modeling of IEEE 802.11 system. [Citation Graph (, )][DBLP]


  995. A concurrent multi-band LNA for multi-standard radios. [Citation Graph (, )][DBLP]


  996. An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. [Citation Graph (, )][DBLP]


  997. Multiple description watermarking for lossy network. [Citation Graph (, )][DBLP]


  998. Directional watermarks in images. [Citation Graph (, )][DBLP]


  999. An error resilient image camouflaging scheme for secret image transmission. [Citation Graph (, )][DBLP]


  1000. Semi-fragile watermarking for text document images authentication. [Citation Graph (, )][DBLP]


  1001. Multiple description coding using multiple reference frame for robust video transmission. [Citation Graph (, )][DBLP]


  1002. Digital watermarking for color video using a nonlinear filter in detection process. [Citation Graph (, )][DBLP]


  1003. Image authentication using content based watermark. [Citation Graph (, )][DBLP]


  1004. Hiding watermark in watermark [image watermarking]. [Citation Graph (, )][DBLP]


  1005. A novel unequal error protection approach for error resilient video transmission. [Citation Graph (, )][DBLP]


  1006. Optimal joint rate and power allocation in a multicell multimedia CDMA network. [Citation Graph (, )][DBLP]


  1007. Audio signal segmentation and classification for scene-cut detection. [Citation Graph (, )][DBLP]


  1008. Drift-free multiple description video coding with redundancy rate-distortion optimization. [Citation Graph (, )][DBLP]


  1009. Optimized multiple description image coding using lattice vector quantization. [Citation Graph (, )][DBLP]


  1010. Low redundancy layered multiple description scalable coding using the subband extension of H.264/AVC. [Citation Graph (, )][DBLP]


  1011. Video error concealment by integrating dynamic programming and adaptive Kalman filtering techniques. [Citation Graph (, )][DBLP]


  1012. Enhancing vocoder performance for music signals. [Citation Graph (, )][DBLP]


  1013. An 8b 240 MS/s 1.36 mm/sup 2/ 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs. [Citation Graph (, )][DBLP]


  1014. Convergence analysis of a background interstage gain calibration technique for pipelined ADCs. [Citation Graph (, )][DBLP]


  1015. Smart AD and DA converters. [Citation Graph (, )][DBLP]


  1016. A low power and low voltage continuous time /spl Sigma//spl Delta/ modulator. [Citation Graph (, )][DBLP]


  1017. Synthesis of sigma delta modulators employing continuous time delays. [Citation Graph (, )][DBLP]


  1018. A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing. [Citation Graph (, )][DBLP]


  1019. Low-voltage micropower multipliers with reduced spurious switching. [Citation Graph (, )][DBLP]


  1020. An area efficient 64-bit square root carry-select adder for low power applications. [Citation Graph (, )][DBLP]


  1021. A low-power and high-throughput implementation of the SHA-1 hash function. [Citation Graph (, )][DBLP]


  1022. Hyperblock formation: a power/energy perspective for high performance VLIW architectures. [Citation Graph (, )][DBLP]


  1023. Ultra low voltage design considerations of SOI SRAM memory cells. [Citation Graph (, )][DBLP]


  1024. Battery voltage prediction for portable systems. [Citation Graph (, )][DBLP]


  1025. CPG-MTA implementation for locomotion control. [Citation Graph (, )][DBLP]


  1026. A spiking silicon central pattern generator with floating gate synapses [robot control applications]. [Citation Graph (, )][DBLP]


  1027. A bio-inspired CNN layer with image processing capabilities. [Citation Graph (, )][DBLP]


  1028. Mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation. [Citation Graph (, )][DBLP]


  1029. Effect of mismatch on a ranked-order extractor array [image processing applications]. [Citation Graph (, )][DBLP]


  1030. Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications]. [Citation Graph (, )][DBLP]


  1031. A Fourier series-based RLC interconnect model for periodic signals. [Citation Graph (, )][DBLP]


  1032. Performance model for inter-chip communication considering inductive cross-talk and cost. [Citation Graph (, )][DBLP]


  1033. RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. [Citation Graph (, )][DBLP]


  1034. High speed current-mode signaling circuits for on-chip interconnects. [Citation Graph (, )][DBLP]


  1035. Capacitive coupling of data and power for 3D silicon-on-insulator VLSI. [Citation Graph (, )][DBLP]


  1036. Accurate decoupling of capacitively coupled buses. [Citation Graph (, )][DBLP]


  1037. Power-aware slack distribution for hierarchical VLSI design. [Citation Graph (, )][DBLP]


  1038. A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation PART-I MOSFETs and CMOS inverters. [Citation Graph (, )][DBLP]


  1039. Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. [Citation Graph (, )][DBLP]


  1040. Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis. [Citation Graph (, )][DBLP]


  1041. CheckSyC: an efficient property checker for RTL SystemC designs. [Citation Graph (, )][DBLP]


  1042. CRPG: a configurable random test-program generator for microprocessors. [Citation Graph (, )][DBLP]

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    Optimal allocation of FACTS devices to enhance total transfer capability using evolutionary programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4175-4178 [Conf]
  1044. Vaibhav Donde, Ian A. Hiskens
    Observed hybrid oscillations in an electrical distribution system. [Citation Graph (0, 0)][DBLP]
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  1045. Garng M. Huang, Nirmal-Kumar C. Nair
    Power flow based allocation procedures for voltage security and transmission losses in deregulated power markets. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4183-4186 [Conf]
  1046. Satish J. Ranade, Ramchander Kolluru, Joydeep Mitra
    Identification of chains of events leading to catastrophic failures of power systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4187-4190 [Conf]
  1047. Nader Samaan, Chanan Singh
    Using genetic algorithms for reliability calculations of complex power systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4191-4195 [Conf]
  1048. William Rosehart, Antony Schellenberg, Laleh Behjat, Pouyan Jazayeri, J. A. Aguado
    Coordinated static stability margin management of inter-regional electricity systems. [Citation Graph (0, 0)][DBLP]
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  1049. Timothy K. Horiuchi, Hisham Abdalla
    An ultrasonic filterbank with spiking neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4201-4204 [Conf]
  1050. Pedro Julián, Andreas G. Andreou, Gert Cauwenberghs, Milutin Stanacevic, David H. Goldberg, Pablo Sergio Mandolesi, Laurence Riddle, Shihab Shamma
    Field test results for low power bearing estimator sensor nodes. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4205-4208 [Conf]
  1051. Gabriel Abadal, Jaume Verd, Jordi Teva, Arantxa Uranga, Nuria Barniol, Jaume Esteve, Marta Duch, Francesc Pérez-Murano
    High-sensitivity capacitive readout system for resonant submicrometer-scale cantilevers based sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4209-4212 [Conf]
  1052. André van Schaik, Shih-Chii Liu
    AER EAR: a matched silicon cochlea pair with address event representation interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4213-4216 [Conf]
  1053. Rock Z. Shi, Timothy K. Horiuchi
    A VLSI model of the bat dorsal nucleus of the lateral lemniscus for azimuthal echolocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4217-4220 [Conf]
  1054. Peter R. Kinget, Aurel A. Lazar, Laszlo T. Toth
    On the robustness of an analog VLSI implementation of a time encoding machine. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4221-4224 [Conf]
  1055. Xiaoyin Xu, Xiaowei Chen, Kuang-Yu Liu, Jinmin Zhu, Xiaobo Zhou, Stephen T. C. Wong
    A computer-based system to analyze neuron images. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4225-4228 [Conf]
  1056. Xiaowei Chen, Stephen T. C. Wong
    Automated dynamic cellular analysis in high throughput drug screens. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4229-4232 [Conf]
  1057. Susu Yao, Keng Pang Lim, Xiao Lin, Susanto Rahardja
    A post-processing algorithm using histogram-driven anisotropic diffusion. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4233-4236 [Conf]
  1058. YoungJae Kim, Takashi Morie
    A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4237-4240 [Conf]
  1059. Birgir Bjorn Saevarsson, Johannes R. Sveinsson, Jon Atli Benediktsson
    Translation invariant combined denoising algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4241-4244 [Conf]
  1060. Vishal Gupta, Gabriel A. Rincón-Mora
    A low dropout, CMOS regulator with high PSR over wideband frequencies. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4245-4248 [Conf]
  1061. Q. X. Zhang, L. Siek
    A new 4.3 ppm/°C voltage reference using standard CMOS process with 1V supply voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4249-4252 [Conf]
  1062. Hongchin Lin, Chao-Jui Liang
    A sub-1V bandgap reference circuit using subthreshold current. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4253-4256 [Conf]
  1063. Simon Rioux, Alain Lacourse, Yvon Savaria, Michel Meunier
    Design methods for CMOS low-current finely tunable voltage references covering a wide output range. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4257-4260 [Conf]
  1064. Mohammad M. Ahmadi, Graham A. Jullien
    A new CMOS charge pump for low voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4261-4264 [Conf]
  1065. Nima Maghari, Omid Shoaei
    A dynamic start-up circuit for low voltage CMOS current mirrors with power-down support. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4265-4268 [Conf]
  1066. Jussi-Pekka Jansson, Antti Mäntyniemi, Juha Kostamovaara
    A delay line based CMOS time digitizer IC with 13 ps single-shot precision. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4269-4272 [Conf]
  1067. Enrique Barajas, Luis Elvira, Miguel A. Méndez, Ferran Martorell, Diego Mateo, José Luis González
    Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4273-4276 [Conf]
  1068. Debashis Mandal, Pradip Mandal
    High voltage tolerant output buffer design for mixed voltage interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4277-4280 [Conf]
  1069. Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori
    A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4281-4284 [Conf]
  1070. Hanjun Jiang, Degang Chen, Randall L. Geiger
    Dither incorporated deterministic dynamic element matching for high resolution ADC test using extremely low resolution DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4285-4288 [Conf]
  1071. Hanqing Xing, Degang Chen, Randall L. Geiger
    A two-step DDEM ADC for accurate and cost-effective DAC testing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4289-4292 [Conf]
  1072. Morio Ikehara, Yuji Kobayashi
    A novel lattice structure of M-channel paraunitary filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4293-4296 [Conf]
  1073. S. C. Chan, K. M. Tsui
    Multi-plet two-channel perfect reconstruction filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4297-4300 [Conf]
  1074. Zhang Lei, Anamitra Makur, Zhu Ce
    Design of 2-channel linear phase filter bank: a lifting approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4301-4304 [Conf]
  1075. Jun Wei Lee, Yong Ching Lim
    A multiplierless filter bank with deep stopband suppression and narrow transition width. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4305-4308 [Conf]
  1076. Sergio L. Netto, Luiz C. R. de Barcellos, Paulo S. R. Diniz
    On a modified structure for cosine-modulated filter banks using the frequency-response masking approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4309-4312 [Conf]
  1077. Shishu Yin, Shang Chow Chan
    Factorization of a class of perfect reconstruction modified DFT filter banks with IIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4313-4316 [Conf]
  1078. S. C. Chan, Z. G. Zhang, K. W. Tse
    A new robust Kalman filter algorithm under outliers and system uncertainties. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4317-4320 [Conf]
  1079. S. C. Chan, H. H. Chen, K. L. Ho
    Adaptive beamforming using uniform concentric circular arrays with frequency invariant characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4321-4324 [Conf]
  1080. Zhongkai Zhang, Tamal Bose, Jacob Gunther
    A unified framework for least square and mean square based adaptive filtering algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4325-4328 [Conf]
  1081. Marcelo J. Bruno, Juan E. Cousseau, Pedro D. Donate
    On reduced complexity IIR adaptive filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4329-4332 [Conf]
  1082. S. C. Chan, Y. Zhou, W. Y. Lau
    Approximate QR-based algorithms for recursive nonlinear least squares estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4333-4336 [Conf]
  1083. Felix Albu, H. K. Kwan
    A new block exact affine projection algorithm [acoustic echo cancellation system example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4337-4340 [Conf]
  1084. Sheng-Yu Peng, Bradley A. Minch, Paul E. Hasler
    A programmable floating-gate bump circuit with variable width. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4341-4344 [Conf]
  1085. Serdar Özoguz, Nüfer Yasin Ates, Ahmed S. Elwakil
    An integrated circuit chaotic oscillator and its application for high speed random bit generation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4345-4348 [Conf]
  1086. Fabio Pareschi, Gianluca Setti, Riccardo Rovatti
    A macro-model for the efficient simulation of an ADC-based RNG. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4349-4352 [Conf]
  1087. Rizwan Murji, M. Jamal Deen
    A low-power wideband frequency doubler in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4353-4356 [Conf]
  1088. Haiyan Shu, Lap-Pui Chau
    Frame layer bit allocation for video transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4357-4360 [Conf]
  1089. Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman
    Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4361-4364 [Conf]
  1090. Peng Yin, Alexis M. Tourapis, Jill Boyce
    Localized weighted prediction for video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4365-4368 [Conf]
  1091. Minqiang Jiang, Nam Ling
    Frame-layer H.264 rate control improvement using Lagrange multiplier and quantizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4369-4372 [Conf]
  1092. Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman
    Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4373-4376 [Conf]
  1093. Gounyoung Kim, Yeong-Yil Yang, Alexandros Eleftheriadis
    Motion-assisted rate control for ME/MC-based codecs [video coding]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4377-4380 [Conf]
  1094. Byunghoo Jung, Yi-Hung Tseng, Jackson Harvey, Ramesh Harjani
    Pulse generator design for UWB IR communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4381-4384 [Conf]
  1095. Anand Gopalan, Tejasvi Das, Clyde Washburn, Ponnathpur R. Mukund
    Use of source degeneration for non-intrusive BIST of RF front-end circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4385-4388 [Conf]
  1096. Hyung-Seuk Kim, Mourad N. El-Gamal
    A 1-V fully integrated CMOS frequency synthesizer for 5-GHz WLAN. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4389-4392 [Conf]
  1097. Byunghoo Jung, Shubha Bommalingaiahnapallya, Ramesh Harjani
    Power optimized LC VCO and mixer co-design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4393-4396 [Conf]
  1098. Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu
    2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4397-4400 [Conf]
  1099. Sayfe Kiaei, Shahin Mehdizad Taleie, Bertan Bakkaloglu
    Low-power high-Q NEMS receiver architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4401-4404 [Conf]
  1100. Jun Cheng, Alex C. Kot, Jun Liu, Hong Cao
    Steganalysis of data hiding in binary text images. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4405-4408 [Conf]
  1101. Foo Say Wei, Xue Feng, Li Mengyuan
    A blind audio watermarking scheme using peak point extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4409-4412 [Conf]
  1102. Kaliappan Gopalan
    Robust watermarking of music signals by cepstrum modification. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4413-4416 [Conf]
  1103. Fan Gu, Zhe-Ming Lu, Jeng-Shyang Pan
    Multipurpose image watermarking in DCT domain using subsampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4417-4420 [Conf]
  1104. Shinji Nakamura, Yasuo Nagazumi
    Programmable matched filter by charge-domain operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4421-4424 [Conf]
  1105. Sami Karvonen, Juha Kostamovaara
    Charge-domain FIR sampler with programmable filtering coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4425-4428 [Conf]
  1106. Yi-Ran Sun, Svante Signell
    Generalized quadrature bandpass sampling with FIR filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4429-4432 [Conf]
  1107. Rafal Karakiewicz, Roman Genov
    Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4433-4436 [Conf]
  1108. Behrouz Nowrouzian, Arthur T. G. Fuller, M. N. S. Swamy
    A novel approach to the exact design of first- and second-order Bode-type variable-amplitude bilinear-LDI switched-capacitor equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4437-4440 [Conf]
  1109. Venkatesh Srinivasan, Jeff Dugger, Paul E. Hasler
    An adaptive analog synapse circuit that implements the least-mean-square learning rule. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4441-4444 [Conf]
  1110. Michael Tse, Octavian Dranga, Herbert H. C. Iu
    Bifurcation in parallel-connected buck converters under current-mode control. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4445-4448 [Conf]
  1111. Jianbing Li, Zhongxia Niu, Dongfiang Zhou, Yujie Shi
    Analysis of series-parallel resonant converter with multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4449-4452 [Conf]
  1112. Gerard Villar, Eduard Alarcón, Jordi Madrenas, Francesc Guinjoan, Alberto Poveda
    Energy optimization of tapered buffers for CMOS on-chip switching power converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4453-4456 [Conf]
  1113. Gerard Villar, Eduard Alarcón, Herminio Martínez, Eva Vidal, Sonia Porta, Francesc Guinjoan, Alberto Poveda
    Multi-mode controller CMOS integrated circuit for switching power converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4457-4460 [Conf]
  1114. Hirak Patangia, Tandi Wijaya, Dennis Gregory
    A multi-level inverter for driving a high voltage display. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4461-4464 [Conf]
  1115. Stephan Lang, Babak Daneshrad
    From architecture to implementation of a wireless, multiple antenna testbed. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4465-4468 [Conf]
  1116. Tord Johnson, Johnny Holmberg
    Nonlinear state-space model of charge-pump based frequency synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4469-4472 [Conf]
  1117. Dinesh Divakaran, Vijay K. Jain
    Channel estimation for a new high performance MIMO STC-OFDM WLAN system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4473-4476 [Conf]
  1118. Jaehyun Baek, Ju Hyung Hong, Myung Hoon Sunwoo
    Novel digital signal processing unit for Ethernet receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4477-4480 [Conf]
  1119. Ediz Çetin, Izzet Kale, Richard C. S. Morling
    Joint compensation of IQ-imbalance and carrier phase synchronization errors in communication receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4481-4484 [Conf]
  1120. S. I. Ahmed, Tad A. Kwasniewski
    An all-digital data recovery circuit optimization using Matlab/Simulink. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4485-4488 [Conf]
  1121. Fredrik Edman, Viktor Öwall
    A scalable pipelined complex valued matrix inversion architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4489-4492 [Conf]
  1122. Michael H. F. Leung, Francis C. M. Lau
    Testing system for measuring and calibrating the transmission power of EDGE mobiles. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4493-4496 [Conf]
  1123. Ryosuke Fujiwara, M. Shida, Akira Maeki, Kenichi Mizugaki, Masaru Kokubo, Masayuki Miyazaki
    Rapid signal acquisition for low-rate carrier-based ultra-wideband impulse radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4497-4500 [Conf]
  1124. Xiaoyu Ruan, Rajendra S. Katti
    On the signed-binary window method [cryptosystem applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4501-4504 [Conf]
  1125. Der-Feng Tseng
    A low-complexity iterative interference suppressor for coded aperiodic spreading CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4505-4508 [Conf]
  1126. Hideaki Okazaki, Chiho Okazaki, Hirohiko Honda, Takuji Kawamoto
    Simulink based model realization for CDMA communication over power lines. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4509-4512 [Conf]
  1127. Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon
    Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4513-4516 [Conf]
  1128. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
    An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4517-4520 [Conf]
  1129. Yan-Chen Lu, Chun-Fu Shen, Chi-Kuang Chen, Ju-Lung Fann
    Performance-driven optimization for video accelerator design [video coding]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4521-4524 [Conf]
  1130. Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin
    A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4525-4528 [Conf]
  1131. Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
    An AMBA-compliant deblocking filter IP for H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4529-4532 [Conf]
  1132. YuLong Fan, ChingYao Huang, YuRu Hong
    Timer based scheduling control algorithm in WLAN for real-time services. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4533-4537 [Conf]
  1133. Kouji Miyata, Akira Taguchi
    A novel MPEG-4 rate control method with spatial resolution conversion for low bit-rate coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4538-4541 [Conf]
  1134. Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo
    A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4542-4545 [Conf]
  1135. Kyusik Chung, Donghyun Kim, Lee-Sup Kim
    A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4546-4549 [Conf]
  1136. Chen-Wei Fan, Feng-Cheng Chang, Hsueh-Ming Hang
    An MPEG-4 IPMPX design and implementation on MPEG-21 test bed. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4550-4553 [Conf]
  1137. Jen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen, Te-Jung Lo
    VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4554-4557 [Conf]
  1138. Sheng-Zen Wang, Ting-An Lin, Tsu-Ming Liu, Chen-Yi Lee
    A new motion compensation design for H.264/AVC decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4558-4561 [Conf]
  1139. Ming-Sui Lee, Mei-Yin Shen, Akio Yoneyama, C. C. Jay Kuo
    DCT-domain image registration techniques for compressed video. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4562-4565 [Conf]
  1140. Mladen Panovic, Andreas Demosthenous
    Architectures for analog motion estimation processors: a comparison. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4566-4569 [Conf]
  1141. Jaewan Bae, Donghyun Kim, Lee-Sup Kim
    An 11M-triangles/sec 3D graphics clipping engine for triangle primitives. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4570-4573 [Conf]
  1142. Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
    A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4574-4577 [Conf]
  1143. Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu
    A two-way SIMD-based reconfigurable computing architecture for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4578-4581 [Conf]
  1144. Haiyan Shu, Lap-Pui Chau
    A new scene change feature for video transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4582-4585 [Conf]
  1145. Kam-Fai Lo, Kin-Man Lam
    A new cubic rate distortion model for low-delay video communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4586-4589 [Conf]
  1146. Tsung-Han Tsai, Yung-Chien Chen
    A robust shot change detection method for content-based retrieval. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4590-4593 [Conf]
  1147. Jen-Hao Yeh, Jun-Cheng Chen, Jin-Hau Kuo, Ja-Ling Wu
    TV commercial detection in news program videos. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4594-4597 [Conf]
  1148. Xiaodan Song, Ching-Yung Lin, Ming-Ting Sun
    Autonomous learning of visual concept models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4598-4601 [Conf]
  1149. Min-wuk Lee, Byeong-Gyu Nam, Ju-Ho Sohn, Namjun Cho, Hyejung Kim, Kwanho Kim, Hoi-Jun Yoo
    A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4602-4605 [Conf]
  1150. Frank H. Hsiao, Terng-Yin Hsu
    A frequency domain equalizer for WLAN 802.11g single-carrier transmission mode. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4606-4609 [Conf]
  1151. Safar Hatami, Reshad Hosseini, Mahmoud Kamarei, Hossein Ahmadi
    Wavelet based fingerprint image enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4610-4613 [Conf]
  1152. Jannick Hammel Nielsen, Pietro Andreani, Piero Malcovati, Andrea Baschirotto
    Technology scaling impact on embedded ADC design for telecom receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4614-4617 [Conf]
  1153. Reza Lotfi, Mohammad Taherzadeh-Sani, Omid Shoaei
    Power consumption issues in high-speed high-resolution pipelined A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4618-4621 [Conf]
  1154. Jaana Riikonen, Mikko Aho, Väinö Hakkarainen, Kari Halonen, Lauri Sumanen
    A 10-bit 400-MS/s 170 mW 4-times interleaved A/D converter in 0.35µm BiCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4622-4625 [Conf]
  1155. Manuel Delgado-Restituto, Jesús Ruiz-Amaya, José Manuel de la Rosa, Juan Francisco Fernández-Bootello, Leila Díez, Rocío del Río Fernandez, Ángel Rodríguez-Vázquez
    An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4626-4629 [Conf]
  1156. Shubha Bommalingaiahnapallya, Ramesh Harjani
    Process tolerant design of N-tone Sigma-Delta converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4630-4633 [Conf]
  1157. Hua Li
    A new CAM based S/S/sup -1/-box look-up table in AES. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4634-4636 [Conf]
  1158. Hua Li, Zac Friggstad
    An efficient architecture for the AES mix columns operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4637-4640 [Conf]
  1159. Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
    A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4641-4644 [Conf]
  1160. Apostolos P. Fournaris, Odysseas G. Koufopavlou
    A new RSA encryption architecture and hardware implementation based on optimized Montgomery multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4645-4648 [Conf]
  1161. Yonghong Yang, Z. Abid, Wei Wang, Z. Zhang, C. Yang
    Efficient multi-prime RSA immune against hardware fault attack. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4649-4652 [Conf]
  1162. Deen Kotturi, Seong-Moo Yoo, John Blizzard
    AES crypto chip utilizing high-speed parallel pipelined architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4653-4656 [Conf]
  1163. Christian Merkwirth, Jörg D. Wichard, Maciej Ogorzalek
    Performance of finite iteration DTCNN with truncated stationary templates [digit recognition example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4657-4660 [Conf]
  1164. Fernando Corinto, Marco Gilli, Pier Paolo Civalleri
    An algorithm for predicting the steady state behavior of binary CNNs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4661-4664 [Conf]
  1165. Sibel Senan, Sabri Arik
    Global exponential stability analysis of delayed cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4665-4668 [Conf]
  1166. Marco Gilli, Michele Bonnin, Fernando Corinto
    On global dynamic behavior of weakly connected cellular nonlinear networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4669-4672 [Conf]
  1167. Norikazu Takahashi, Tetsuo Nishi
    On complete stability of three-cell CNNs with opposite-sign templates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4673-4676 [Conf]
  1168. Mauro Di Marco, Mauro Forti, Massimo Grazzini, Luca Pancioni
    Complex dynamics in a class of nearly-symmetric competitive CNNs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4677-4680 [Conf]
  1169. David Levacq, Vincent Dessard, Denis Flandre
    Ultra-low power flip-flops for MTCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4681-4684 [Conf]
  1170. Massimo Alioto, Gaetano Palumbo
    Design techniques for low-power cascaded CML gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4685-4688 [Conf]
  1171. Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
    A low-power and high-speed quaternary interconnection link using efficient converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4689-4692 [Conf]
  1172. JunYoung Park, Sung Je Hong, Jong Kim
    Energy-saving design technique achieved by latched pass-transistor adiabatic logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4693-4696 [Conf]
  1173. Walid Elgharbawy, Pradeep Golconda, Ashok Kumar, Magdy Bayoumi
    A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4697-4700 [Conf]
  1174. Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai
    More than two orders of magnitude leakage current reduction in look-up table for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4701-4704 [Conf]
  1175. Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja
    Generation and properties of new fastest linearly independent transforms over GF(2) with reordering. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4705-4708 [Conf]
  1176. Bogdan J. Falkowski, Cheng Fu
    Properties and relations of ternary linearly independent transforms [multivalued logic applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4709-4712 [Conf]
  1177. Youngsoo Shin, Hyung-Ock Kim
    Analysis of power consumption in VLSI global interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4713-4716 [Conf]
  1178. Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin
    A divide-and-conquer approach to estimating minimum/maximum leakage current. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4717-4720 [Conf]
  1179. Malgorzata Chrzanowska-Jeske, Alan Mishchenko
    Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4721-4724 [Conf]
  1180. Meng-Chiou Wu, Rung-Bin Lin
    Multiple project wafers for medium-volume IC production. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4725-4728 [Conf]
  1181. Kazuhiko Koeda, Hiroshi Sasaki, Teppei Ueyama, Yoshifumi Zoka, Naoto Yorino
    A study on distribution network planning with considering customer's utilization of distributed generators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4729-4732 [Conf]
  1182. Yuji Mishima, Kensaku Sugawara, Taiji Satoh, Koichi Nara
    Three-phase power flow for FRIENDS network. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4733-4736 [Conf]
  1183. Takeshi Nagata, Yoshiki Tahara, Hideki Fujita
    An agent approach to power system distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4737-4742 [Conf]
  1184. Shiqiong Tong, Michael Kleinberg, Karen Miu
    A distributed slack bus model and its impact on distribution system application techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4743-4746 [Conf]
  1185. Hiroyuki Mori, Shingo Tsunokawa
    Variable neighborhood tabu search for capacitor placement in distribution systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4747-4750 [Conf]
  1186. Toshiaki Mori, Akio Furuta
    A new approach of hierarchical optimization to distribution system service restoration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4751-4754 [Conf]
  1187. Timothy K. Horiuchi
    A low-power visual horizon estimation chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4755-4758 [Conf]
  1188. David Claveau, Chunyan Wang
    A spatial variance approach to target tracking with sensor arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4759-4762 [Conf]
  1189. Narrijun Cho, Seong-Jun Song, Jae-Youl Lee, Sunyoung Kim, Shiho Kim, Hoi-Jun Yoo
    A 8-µW, 0.3-mm2 RF-powered transponder with temperature sensor for wireless environmental monitoring. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4763-4766 [Conf]
  1190. Mounir Boukadoum, Karima Tabari, Abdelhak Bensaoula, David Starikov, El Mostapha Aboulhamid
    FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4767-4770 [Conf]
  1191. Ralf M. Philipp, Ralph Etienne-Cummings
    A 1V current-mode CMOS active pixel sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4771-4774 [Conf]
  1192. Matthew A. Clapp, Ralph Etienne-Cummings
    Sonar echo-location in 2-D using mini-microphone array and spatiotemporal frequency filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4775-4778 [Conf]
  1193. See-Kiong Ng
    Smart bio-laboratories of the future. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4779-4782 [Conf]
  1194. Xiaolin Zhang
    A conceptual discussion on relationship between vergence and conjugate eye movements on the viewpoint of system and control engineering. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4783-4786 [Conf]
  1195. Xiaobo Zhou, Stephen T. C. Wong
    Dynamic sub-cellular behavior study in high content imaging using a multi-threshold approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4787-4790 [Conf]
  1196. Luonan Chen, Ruiqi Wang, Zhujun Jing, Kazuyuki Aihara
    Cooperative dynamics coordinated by stochastic noise in a multi-cell system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4791-4794 [Conf]
  1197. Diego Ruben Barrettino, Barry Lutz, Maria Elena Martin, Sarah McQuaide, Deirdre R. Meldrum
    CMOS readout and control architecture for single-cell real-time microsystems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4795-4798 [Conf]
  1198. Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Achutavarrier Prasad Vinod
    A reconfigurable architecture for scanning biosequence databases. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4799-4802 [Conf]
  1199. Jin-Hong Hwang, Mi-Young Lee, Chan-Young Jeong, Changsik Yoo
    Active-RC channel selection filter tunable from 6 kHz to 18 MHz for software-defined radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4803-4806 [Conf]
  1200. H. Feng, Q. Wu, X. Guan, R. Zhan, A. Wang, L.-W. Yang
    A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35µm SiGe BiCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4807-4810 [Conf]
  1201. Ram Singh Rana, Xiangdong Zhou, Yong Lian
    An optimized 2.4 GHz CMOS LC-tank VCO with 0.55 %/V frequency pushing and 516 MHz tuning range. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4811-4814 [Conf]
  1202. Wei Meng Lim, Han Guo Ma, Manh Anh Do, Kiat Seng Yeo
    A 5GHz to 6GHz integrated differential LNA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4815-4818 [Conf]
  1203. Huseyin Dinc, Phillip E. Allen, Sudipto Chakraborty
    A low distortion, current feedback, programmable gain amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4819-4822 [Conf]
  1204. Shengyuan Li, Huseyin Dinc, Susanta Sengupta, Phillip E. Allen
    A high-speed wide-range low-distortion constant-gm cell design for GHz applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4823-4826 [Conf]
  1205. Mladen Panovic, Andreas Demosthenous
    A low power block-matching analog motion estimation processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4827-4830 [Conf]
  1206. Xin Dai, Degang Chen, Randall L. Geiger
    A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4831-4834 [Conf]
  1207. Xin Dai, Chengming He, Hanqing Xing, Degang Chen, Randall L. Geiger
    An N/sup th/ order central symmetrical layout pattern for nonlinear gradients cancellation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4835-4838 [Conf]
  1208. Athon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund
    A flexible ADC approach for mixed-signal SoC platforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4839-4842 [Conf]
  1209. Jerzy Dabrowski, Javier Gonzalez Bayon
    Techniques for sensitizing RF path under SER test. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4843-4846 [Conf]
  1210. Carl Chun, Youngsik Hur, Moonkyun Maeng, Hyoungsoo Kim, Soumya Chandramouli, Edward Gebara, Joy Laskar
    A 0.18µm-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4847-4850 [Conf]
  1211. Feng Li, Kyohei Ishihata, Jianming Lu, Takashi Yahagi
    Perfect tracking control using multirate control in magnetic levitation system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4851-4854 [Conf]
  1212. Nobuhiko Sugino, Tomoyuki Matsuura, Akinori Nishihara
    New graph transformation schemes in graph-based memory allocation method for an indirect addressing DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4855-4858 [Conf]
  1213. Max-Elie Salomon, Abdelhakim Khouas, Yvon Savaria
    A complete spurs distribution model for direct digital period synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4859-4862 [Conf]
  1214. Peter Lee
    An evaluation of a hybrid-logarithmic number system DCT/IDCT algorithm [image compression applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4863-4866 [Conf]
  1215. Chun-Yat Ma, Tai-Chiu Hsung, Daniel Pak-Kong Lun
    Efficient realization for symmetric orthogonal multiwavelet by simple scaling and rotation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4867-4870 [Conf]
  1216. Yu-Chun Peng, Hung-An Chang, Chia-Kai Liang, Homer Chen, Chang-Jung Kao
    Integration of image stabilizer with video codec for digital video cameras. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4871-4874 [Conf]
  1217. Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
    An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4875-4878 [Conf]
  1218. Wen Tsern Ho, Mourad N. El-Gamal
    Fully-differential 13 Gbps clock recovery circuit for OC-255 SONET applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4879-4882 [Conf]
  1219. Ming-Ta Hsieh, Gerald E. Sobelman
    Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4883-4886 [Conf]
  1220. Xu Chen, Jin Liu
    A delay compensation technique for n-phase clock generation with 2(N-1) delay units. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4887-4890 [Conf]
  1221. Brian Welch, Jing-Hong Zhan, Kevin Kornegay
    A family of SiGe quadrature oscillators for microwave applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4891-4894 [Conf]
  1222. Ching-Chi Chang, Chorng-Kuang Wang
    High speed pilot-less sampling frequency acquisition for DMT systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4895-4898 [Conf]
  1223. Serkan Günel, F. Acar Savaci
    Approximate stationary density of the nonlinear dynamical systems excited with white noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4899-4902 [Conf]
  1224. Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
    Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4903-4906 [Conf]
  1225. Chikashi Nakazawa, Shinji Kitagawa, Yoshikazu Fukuyama, Hsiao-Dong Chiang
    A method for searching multiple local optimal solutions of nonlinear optimization problems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4907-4910 [Conf]
  1226. Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue
    An efficient homotopy method for finding DC operating points of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4911-4914 [Conf]
  1227. Federico Bizzarri, Marco Storace, Mauro Parodi
    SVD-based approximations of bivariate functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4915-4918 [Conf]
  1228. Xueqin Zhao, Jianming Lu, Takashi Yahagi
    A design method for parallel recursive least square adaptive Volterra filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4919-4922 [Conf]
  1229. Tak-Song Chong, Oscar C. Au, Wing-San Chau, Tai-Wai Chan
    A content adaptive de-interlacing algorithm [video signal processing applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4923-4926 [Conf]
  1230. Jiefu Zhai, Keman Yu, Jiang Li, Shipeng Li
    A low complexity motion compensated frame interpolation method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4927-4930 [Conf]
  1231. Takahiro Ogawa, Miki Haseyama, Hideo Kitajima
    Restoration method of missing areas in still images using GMRF model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4931-4934 [Conf]
  1232. Md. Imamul Hassan Bhuiyan, M. Omair Ahmad, M. N. S. Swamy
    A new homomorphic Bayesian wavelet-based MMAE filter for despeckling SAR images. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4935-4938 [Conf]
  1233. Xiaokang Yang, Susu Yao, Keng Pang Lim, Xiao Lin, Susanto Rahardja, Feng Pan
    An adaptive edge-preserving artifacts removal filter for video post-processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4939-4942 [Conf]
  1234. Nikhil Gupta, M. N. S. Swamy, Eugene I. Plotkin
    Bayesian algorithm for video noise reduction in the wavelet domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4943-4946 [Conf]
  1235. Zhan Guo, Peter Nilsson
    A 53.3 Mb/s 4×4 16-QAM MIMO decoder in 0.35-µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4947-4950 [Conf]
  1236. Jongsoo Choi, Tet Hin Yeap, Martin Bouchard
    Adaptive filtering-based iterative channel estimation for MIMO wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4951-4954 [Conf]
  1237. Rongtao Xu, Francis C. M. Lau
    Performance analysis for MIMO systems using zero forcing detector over Rice fading channel. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4955-4958 [Conf]
  1238. Tong Zhang, Yan Xin, Sizhong Chen
    Parallelism/regularity-driven MIMO detection algorithm design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4959-4962 [Conf]
  1239. Yongtao Wang, Kaushik Roy
    A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4963-4966 [Conf]
  1240. Rongtao Xu, Francis C. M. Lau
    Degradation on the performance of MIMO system under a correlated sub-channels condition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4967-4970 [Conf]
  1241. Dekun Zou, Yun Q. Shi
    Formatted text document data hiding robust to printing, copying and scanning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4971-4974 [Conf]
  1242. Feng-Hsing Wang, Jeng-Shyang Pan, Lakhmi C. Jain
    Shadow watermark embedding system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4975-4978 [Conf]
  1243. Yueh-Hong Chen, Jun-Min Su, H.-C. Fu, Hsiang-Cheh Huang, Hsiao-Tien Pao
    Adaptive watermarking using relationships between wavelet coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4979-4982 [Conf]
  1244. Feng-Cheng Chang, Hsiang-Cheh Huang, Hsueh-Ming Hang
    Layered access control schemes on watermarked scalable media. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4983-4986 [Conf]
  1245. Yusuke Seki, Hiroyuki Kobayashi, Masaaki Fujiyoshi, Hitoshi Kiya
    Quantization-based image steganography without data hiding position memorization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4987-4990 [Conf]
  1246. Shu-Kei Yip, Oscar C. Au
    Digital watermarking using Walsh code sequences with error spreading technique and intra-pixel prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4991-4994 [Conf]
  1247. Xiang Xie, GuoLin Li, Zhihua Wang, Chun Zhang, Dongmei Li, Xiaowen Li
    A novel method of lossy image compression for digital image sensors with Bayer color filter arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4995-4998 [Conf]
  1248. Chi-Leung San, Chiu-sing Choy, Pak-Kee Chan, Cheong-fat Chan, Kong-Pang Pun
    Realization of card-centric framework: a card-centric computer [smart cards]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4999-5002 [Conf]
  1249. Markus Helfenstein, Ertan Baykal, Kurt Müller, Alexander Lampe
    Error vector magnitude (EVM) measurements for GSM/EDGE applications revised under production conditions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5003-5006 [Conf]
  1250. Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao
    A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5007-5010 [Conf]
  1251. Liang Chen, Charles Grant Brown
    A 3D mouse for interacting with virtual objects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5011-5014 [Conf]
  1252. Wen-Chung Kao, Tai-Hua Sun, Sheng-Yuan Lin
    A robust embedded software platform for versatile camera systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5015-5018 [Conf]
  1253. Yun-Nan Chang
    Design of an efficient memory-based DVB-T channel decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5019-5022 [Conf]
  1254. Lu Liu, Zhihua Wang
    A new high gain low voltage 1.45 GHz CMOS mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5023-5026 [Conf]
  1255. X. P. Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo
    A new 5 GHz CMOS dual-modulus prescaler. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5027-5030 [Conf]
  1256. Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
    A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5031-5034 [Conf]
  1257. Kaixue Ma, Hanguo Ma, Haobin Zhang, Gao Wei
    A 23 GHz high isolation sub-harmonic mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5035-5038 [Conf]
  1258. Gaurav Chandra, Anant Kamath, Prakash Easwaran
    A current mode 2.4 GHz direct conversion receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5039-5042 [Conf]
  1259. Chi-Fang Li, Kuo-Hua Pu, Yuan-Sun Chu
    An integrated pseudo-noise code acquisition processor for WCDMA, CDMA2000 and 802.11b systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5043-5046 [Conf]
  1260. Iwata Sakagami
    Derivation of two- and three-branch lumped element codirectional couplers and their frequency characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5047-5050 [Conf]
  1261. Kuan-Hung Chen, Tzi-Dar Chiueh
    Low-complexity adaptive algorithms for pre-distortion of power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5051-5054 [Conf]
  1262. Srikanth Arekapudi, Echere Iroaga, Boris Murmann
    A low-power distributed wide-band LNA in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5055-5058 [Conf]
  1263. Jussi Ryynänen, Mikko Hotti, Kari Halonen
    IIP2 calibration methods for current output mixer in direct-conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5059-5062 [Conf]
  1264. Chang-Ching Wu, Mei-Fen Chou, Wen-Shen Wuen, Kuei-Ann Wen
    A low power CMOS low noise amplifier for ultra-wideband wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5063-5066 [Conf]
  1265. Yanxin Wang, Jon S. Duster, Kevin T. Kornegay
    Design of an ultra-wideband low noise amplifier in 0.13µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5067-5070 [Conf]
  1266. Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, Jatinder Chana
    Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5071-5074 [Conf]
  1267. Giuseppe de Vita, Giuseppe Iannaccone
    Ultra low power RF section of a passive microwave RFID transponder in 0.35µm BiCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5075-5078 [Conf]
  1268. Chung-Yu Wu, Chi-Yao Yu
    A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5079-5082 [Conf]
  1269. Troels Studsgaard Nielsen, Saska Lindfors, Shady Shawky Tawfik, Torben Larsen
    Modeling power amplifiers with antenna mismatch. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5083-5086 [Conf]
  1270. Lei Zhou, Yong Ping Xu, Fujiang Lin
    A gigahertz wideband CMOS multiplier for UWB transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5087-5090 [Conf]
  1271. Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai
    A high-frequency phase-compensation fractional-N frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5091-5094 [Conf]
  1272. Yunlei Li, Jin Liu
    A 13.56 MHz RFID transponder front-end with merged load modulation and voltage doubler-clamping rectifier circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5095-5098 [Conf]
  1273. Yang-Chaun Chen, Chien-Nan Kuo
    A 6-10-GHz ultra-wideband tunable LNA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5099-5102 [Conf]
  1274. Sripriya R. Bandi, Clyde Washburn, P. R. Mukund, Jan Kolnik, Minxuan Liu, Ken Paradis, Steve Howard, Jeff Burleson
    Accurate performance prediction of multi-GHz CML with data run-length variations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5103-5106 [Conf]
  1275. Reza Molavi, Shahriar Mirabbasi, Majid Hashemi
    A wideband CMOS LNA design approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5107-5110 [Conf]
  1276. Sajay Jose, Hyung-Jin Lee, Dong Ha, Sangsung Choi
    A low-power CMOS power amplifier for ultra wideband (UWB) applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5111-5114 [Conf]
  1277. Mallesh Rajashekharaiah, Parag Upadhyaya, Deuk Hyoun Heo, Yi-Jan Emery Chen
    A new gain controllable on-chip active balun for 5 GHz direct conversion receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5115-5118 [Conf]
  1278. Yu-Luen Chen, Weoi-Luen Chen, Chin-Chih Hsiao, Te-Son Kuo, Jin-Shin Lai
    Development of the FES system with neural network + PID controller for the stroke. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5119-5121 [Conf]
  1279. Chia-Feng Juang, Chyi-Tian Chiou, Hao-Jung Huang
    Noisy speech recognition by hierarchical recurrent neural fuzzy networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5122-5125 [Conf]
  1280. Jigme Singye, Katsumi Masugata, Tadakuni Murai, Iwao Kitamura, Honda Kontani
    Thunderstorm tracking system using neural networks and measured electric fields from few field mills. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5126-5129 [Conf]
  1281. Jiunshian Phuah, Jianming Lu, Muhammad Yasser, Takashi Yahagi
    Neuro-sliding mode control for magnetic levitation systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5130-5133 [Conf]
  1282. Alessio Titti, Stefano Squartini, Francesco Piazza
    A new time-variant neural based approach for nonstationary and non-linear system identification. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5134-5137 [Conf]
  1283. Mohammed A. Hasan
    Natural gradient for minor component extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5138-5141 [Conf]
  1284. Cesare Alippi, Fabio Scotti
    Exploiting application locality to design fast, low power, low complexity neural classifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5142-5145 [Conf]
  1285. Raungrong Suleesathira, Sunisa Kunarak
    Neural network handoff in shadow-Rayleigh fading. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5146-5149 [Conf]
  1286. Dylan R. Muir, Giacomo Indiveri, Rodney J. Douglas
    Form specifies function: robust spike-based computation in analog VLSI without precise synaptic weights. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5150-5153 [Conf]
  1287. Faisal M. Khan, Mark G. Arnold, William M. Pottenger
    Hardware-based support vector machine classification in logarithmic number systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5154-5157 [Conf]
  1288. Linlin Yang, Zhenan Huang, Wenbo Wang
    Fuzzy logic based handover in MC-CDMA system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5158-5161 [Conf]
  1289. Phanom Petchjatuporn, Phinyo Wicheanchote, Noppadol Khaehintung, Wiwat Kiranon, Khamron Sunat, Sirapat Chiewchanwattana
    Intelligent ultra fast charger for Ni-Cd batteries. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5162-5165 [Conf]
  1290. Alain Vachoux, Christoph Grimm, Karsten Einwich
    Extending SystemC to support mixed discrete-continuous system modeling and simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5166-5169 [Conf]
  1291. Trent McConaghy, Georges G. E. Gielen
    IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5170-5173 [Conf]
  1292. Peter Wilson, Reuben Wilcock
    Behavioural modeling and simulation of a switched-current phase locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5174-5177 [Conf]
  1293. Gabriel Popescu, Leonid B. Goldgeisser
    Modeling and simulation of mixed signal systems using a multi-lingual simulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5178-5181 [Conf]
  1294. Vanco B. Litovski, Mark Zwolinski, Miona Andrejevic
    Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5182-5185 [Conf]
  1295. H. Alan Mantooth, Xiaoling Huang, Yucheng Feng, W. Zheng
    Ascend: automatic bottom-up behavioral modeling tool for analog circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5186-5189 [Conf]
  1296. Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
    Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5190-5193 [Conf]
  1297. Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
    Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5194-5197 [Conf]
  1298. Yijun Li, Mohamed A. Elgamel, Magdy A. Bayoumi
    A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5198-5201 [Conf]
  1299. Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5202-5205 [Conf]
  1300. Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
    Encoding circuits for low power optical on-chip communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5206-5209 [Conf]
  1301. José L. Rodríguez-Navarro, Michael Gansen, Tobias G. Noll
    Error-tolerant FIR filters based on low-cost residue codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5210-5213 [Conf]
  1302. Paolo Arena, Luigi Fortuna, Mattia Frasca, Luca Patané, M. Pavone
    Climbing obstacles via bio-inspired CNN-CPG and adaptive attitude control. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5214-5217 [Conf]
  1303. Christian Niederhöfer, Ronald Tetzlaff
    Recent results on the prediction of EEG signals in epilepsy by discrete-time cellular neural networks (DTCNN). [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5218-5221 [Conf]
  1304. Dávid Bálya, Botond Roska
    Retina model with real time implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5222-5225 [Conf]
  1305. Leila Shepherd, Chris Toumazou
    Towards an implantable ultra-low power biochemical signal processor for blood and tissue monitoring. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5226-5229 [Conf]
  1306. Stanley Y. M. Lam, Bertram Emil Shi, Kwabena Boahen
    Self-organized cortical map formation by guiding connections. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5230-5233 [Conf]
  1307. Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani
    An efficient model for performance analysis of asynchronous pipeline design methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5234-5237 [Conf]
  1308. Ilya Obridko, Ran Ginosar
    Low energy asynchronous architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5238-5241 [Conf]
  1309. Valentin Gies, Thierry M. Bernard, Alain Mérigot
    Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5242-5245 [Conf]
  1310. Bo Zhou, Abdelhakim Khouas
    Measurement of delay mismatch due to process variations by means of modified ring oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5246-5249 [Conf]
  1311. Seiji Miura, Satoru Akiyama
    A memory controller that reduces latency of cached SDRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5250-5253 [Conf]
  1312. Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu
    Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5254-5257 [Conf]
  1313. G. Y. Liu, N. C. Wang, J. B. Kuo
    Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5258-5261 [Conf]
  1314. A. Pouladi, Saeid Nooshabadi
    Opcode encoding for low power embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5262-5265 [Conf]
  1315. Mauro Olivieri, Mirko Scarana, Simone Smorfa
    Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5266-5269 [Conf]
  1316. Tay Teng Tiow, Zhu Xiaoping
    A runtime auto scalable power-efficient instruction-cache design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5270-5273 [Conf]
  1317. Wei Han, Ahmet T. Erdogan, Tughrul Arslan, M. Hasan
    Low power commutator for pipelined FFT processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5274-5277 [Conf]
  1318. Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha
    A low-power scan-path architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5278-5281 [Conf]
  1319. Bei Gou
    Extension of observability analysis to Hachtel's augmented matrix [power system analysis applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5282-5285 [Conf]
  1320. Yoshihiko Kataoka
    A smooth power flow model of electric power system with generator reactive power limits taken into consideration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5286-5289 [Conf]
  1321. Elsaid Elsayed El-Araby, Naoto Yorino, Yoshifumi Zoka
    Optimal procurement of VAR ancillary service in the electricity market considering voltage security. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5290-5293 [Conf]
  1322. Luciano V. Barboza, André Arthur Perleberg Lerm, Roberto S. Salgado
    Unsolvable power flow - restoring solutions of the electric power network equations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5294-5297 [Conf]
  1323. Jung-Wook Park, Ian A. Hiskens
    Damping improvement through tuning controller limits of a series FACTS device. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5298-5301 [Conf]
  1324. Qingyan Liu, Chika O. Nwankpa
    Applications of operational transconductance amplifier in power system analog emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5302-5305 [Conf]
  1325. Chen Shoushun, Amine Bermak
    A low power CMOS imager based on time-to-first-spike encoding and fair AER. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5306-5309 [Conf]
  1326. Alexander Fish, Shy Hamami, Orly Yadid-Pecht
    Self-powered active pixel sensors for ultra low-power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5310-5313 [Conf]
  1327. Eric Liu Wong, Pamela Abshire, Marc H. Cohen
    A 128×128 floating gate imager with self-adapting fixed pattern noise reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5314-5317 [Conf]
  1328. Abhishek Bandyopadhyay, Jungwon Lee, Ryan W. Robucci, Paul E. Hasler
    A 80µW/frame 104×128 CMOS imager front end for JPEG compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5318-5321 [Conf]
  1329. Zhiqiang Lin, Michael W. Hoffman, Walter D. Leon-Salas, Nathan Schemm, Sina Balkir
    A CMOS image sensor for focal plane decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5322-5325 [Conf]
  1330. Graham R. Nelson, Graham A. Jullien, Orly Yadid-Pecht
    CMOS image sensor with watermarking capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5326-5329 [Conf]
  1331. Takashi Matsuo, Shuji Maekawa
    Field test of the world first 200 Mbps PLC modems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5330-5332 [Conf]
  1332. Yoshihiro Ohtani, Susumu Kitaguchi, Toru Ueda, Toru Chiba
    QoS technologies on AV/CE-oriented wireless home network. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5333-5336 [Conf]
  1333. Ikuo Keshi, Yumi Shiraishi, Hiroaki Niwamoto, Minoru Okada, Heiichi Yamamoto
    Is home network application acceptable or not? [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5337-5340 [Conf]
  1334. H. Ikebe, K. Ogawa, H. Takernura, Y. Hatayama
    New architecture of realizing seamless connectivity and cooperative control for home network systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5341-5344 [Conf]
  1335. T. Matsumura, N. Iwanaga, Takao Onoye, Wataru Kobayashi, Isao Shirakawa, Itthichai Arungsrisangchai
    3D sound movement system for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5345-5348 [Conf]
  1336. S. Kamae, Takahiro Irita, A. Tsukimori, S. Tarnaki, Toshihiro Hattori, Shinichi Yoshioka
    SH-mobile - low power application processor for cellular [3G cellular phones]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5349-5352 [Conf]
  1337. Miguel A. Martins, Koen van Hartingsveldt, Chris J. M. Verhoeven, Jorge R. Fernandes
    A wide-band low-noise amplifier with double loop feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5353-5356 [Conf]
  1338. Sumit Bagga, Sandro A. P. Haddad, Koen van Hartingsveldt, Simon Lee, Wouter A. Serdijn, John R. Long
    An interference rejection filter for an ultra-wideband quadrature downconversion autocorrelation receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5357-5360 [Conf]
  1339. Arantxa Uranga, Nuria Barniol, Humberto Campanella, PinedaJaume Esteve Tintó, Lluís Terés, Zachary Davis
    A read-out strategy and circuit design for high frequency MEMS resonators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5361-5364 [Conf]
  1340. Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata
    A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5365-5368 [Conf]
  1341. Holly Pekau, Lee Hartley, James W. Haslett
    A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5369-5372 [Conf]
  1342. Sreenath Thoka, Randall L. Geiger
    Fast-switching adaptive bandwidth frequency synthesizer using a loop filter with switched zero-resistor array. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5373-5376 [Conf]
  1343. Mikko Saukoski, Lasse Aaltonen, Teemu Salo, Kari Halonen
    Fully integrated charge sensitive amplifier for readout of micromechanical capacitive sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5377-5380 [Conf]
  1344. Mikko Saukoski, Lasse Aaltonen, Kari Halonen
    Fully integrated charge pump for high voltage excitation of a bulk micromachined gyroscope. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5381-5384 [Conf]
  1345. Marco Grassi, Piero Malcovati, Andrea Baschirotto
    Flexible high-accuracy wide-range gas sensor interface for portable environmental nosing purpose. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5385-5388 [Conf]
  1346. Mehdi Jafaripanah, Bashir M. Al-Hashimi, Neil M. White
    Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5389-5392 [Conf]
  1347. Massimo Panella, Maurizio Paschero, Fabio Massimo Frattale Mascioli
    A modular RC-active network for vibration damping in piezo-electro-mechanical beams. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5393-5396 [Conf]
  1348. Yuan Ma, Xiqun Zhu, Robert W. Newcomb
    Cost effective high voltage driver for large channel count optical MEMS switch applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5397-5400 [Conf]
  1349. Teerayoot Sawangsri, Vorapoj Patanavijit, Somchai Jitapunkul
    Face segmentation based on Hue-Cr components and morphological technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5401-5404 [Conf]
  1350. Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang
    A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5405-5408 [Conf]
  1351. Gaoming Huang, Luxi Yang, Zhenya He
    Time-delay direction finding based on canonical correlation analysis [electronic warfare applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5409-5412 [Conf]
  1352. Isao Nakanishi, Hiroyuki Sakamoto, Yoshio Itoh, Yutaka Fukui
    DWT domain multi-matcher on-line signature verification system. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5413-5416 [Conf]
  1353. Augusto Santiago Cerqueira, Carlos Augusto Duque, Rogério Marques Trindade, M. V. Ribeiro
    Digital system for detection and classification of electrical events. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5417-5420 [Conf]
  1354. Lin Zhiwei, A. Benjamin Premkumar, A. S. Madhukumar
    Tap selection based MMSE equalization for high data rate UWB communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5421-5424 [Conf]
  1355. Mitsuhiro Matsuo, Masaru Kamada, Hiromasa Habuchi
    Design of UWB pulses based on B-splines. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5425-5428 [Conf]
  1356. A. Prasad Vinod, Edmund Ming-Kit Lai
    Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5429-5432 [Conf]
  1357. You Zheng, Carlos E. Saavedra
    A BPSK demodulator circuit using an anti-parallel synchronization loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5433-5436 [Conf]
  1358. Archana Chidanandan, Magdy A. Bayoumi
    Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5437-5440 [Conf]
  1359. Yao Gang, Tughrul Arslan, Ahmet T. Erdogan
    An efficient pre-traceback approach for Viterbi decoding in wireless communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5441-5444 [Conf]
  1360. Marcus Prochaska, Wolfgang Mathis, Alexander Belski
    Bifurcation analysis of on-chip LC VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5445-5448 [Conf]
  1361. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
    A scalable DCO design for portable ADPLL designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5449-5452 [Conf]
  1362. Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg
    A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5453-5456 [Conf]
  1363. Cameron T. Charles, David J. Allstot
    A 360° extended range phase detector for type-I PLLs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5457-5460 [Conf]
  1364. Krishnakumar Sundaresan, Paul S. Ho, Siavash Pourkamali, Farrokh Ayazi
    A two-chip, 4-MHz, microelectromechanical reference oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5461-5464 [Conf]
  1365. Behzad Mesgarzadeh, Atila Alvandpour
    A study of injection locking in ring oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5465-5468 [Conf]
  1366. Yu-Wen Huang, Chia-Lin Lee, Ching-Yeh Chen, Liang-Gee Chen
    One-pass computation-aware motion estimation with adaptive search strategy. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5469-5472 [Conf]
  1367. Zhi Yang, Hua Cai, Jiang Li
    A framework for fine-granular computational-complexity scalable motion estimation [real-time video coding applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5473-5476 [Conf]
  1368. Hoi-Ming Wong, Oscar C. Au, Andy Chang
    Fast sub-pixel inter-prediction - based on texture direction analysis (FSIP-BTDA) [video coding applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5477-5480 [Conf]
  1369. Gwo-Long Li, Mei-Juan Chen, Hung-Ju Li, Ching-Ting Hsu
    Efficient search and mode prediction algorithms for motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5481-5484 [Conf]
  1370. Xuan-Quang Banh, Yap-Peng Tan
    Efficient video motion estimation using dual-cross search algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5485-5488 [Conf]
  1371. Xiaoquan Yi, Nam Ling
    Rapid block-matching motion estimation using modified diamond search algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5489-5492 [Conf]
  1372. Ge Yang, Yong Sin Kim, Sung-Mo Kang
    Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5493-5496 [Conf]
  1373. Stefano Marsili
    Algorithm for peak to average power ratio reduction operating at symbol rate. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5497-5500 [Conf]
  1374. Day-Uei Li, Li-Ren Huang, Chia-Ming Tsai
    A 3.5-Gb/s CMOS burst-mode laser driver with automatic power control using single power supply. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5501-5504 [Conf]
  1375. Svetoslav Radoslavov Gueorguiev, Saska Lindfors, Torben Larsen
    Common-mode stability in low-power LO drivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5505-5508 [Conf]
  1376. Cesare Alippi, Giovanni Vanini
    An application-level methodology to guide the design of intelligent-processing, power-aware passive RFIDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5509-5512 [Conf]
  1377. C. Huggett, K. Maharatna, K. Paul
    On the implementation of 128-pt FFT/IFFT for high-performance WPAN. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5513-5516 [Conf]
  1378. Chao-Yong Hsu, Chun-Shien Lu
    Near-perfect cover image recovery anti-multiple watermark embedding approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5517-5520 [Conf]
  1379. Chai Wah Wu
    Privacy preserving data mining with unidirectional interaction. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5521-5524 [Conf]
  1380. Wei-Gang Fu, Wei-Qi Yan, Mohan S. Kankanhalli
    Progressive scrambling for MP3 audio. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5525-5528 [Conf]
  1381. In Koo Kang, Choong-Hoon Lee, Hae-Yeoun Lee, Jong-Tae Kim, Heung-Kyu Lee
    Averaging attack resilient video fingerprinting. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5529-5532 [Conf]
  1382. Dahua Xie, C. C. Jay Kuo
    Multimedia data encryption via random rotation in partitioned bit streams. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5533-5536 [Conf]
  1383. Hyoung Joong Kim, Yongsoo Choi
    A new visual cryptography using natural images. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5537-5540 [Conf]
  1384. Pieter Harpe, Athon Zanikopoulos, Arthur H. M. van Roermund
    Digital self-correction of time-interleaved ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5541-5544 [Conf]
  1385. A. Seedher, Preetam Tadeparthy, K. A. S. Satheesh, V. T. Anuroop
    Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5545-5548 [Conf]
  1386. Walter D. Leon, Sina Balkir, Khalid Sayood, Michael W. Hoffman
    An analog-to-digital converter with Golomb-Rice output codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5549-5552 [Conf]
  1387. Erhan Ozalevli, Christopher M. Twigg, Paul E. Hasler
    10-bit programmable voltage-output digital-analog converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5553-5556 [Conf]
  1388. Echere Iroaga, Boris Murmann, L. Y. Nathawad
    A background correction technique for timing errors in time-interleaved analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5557-5560 [Conf]
  1389. Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada
    Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5561-5564 [Conf]
  1390. Tudor Petrescu, Jacques Oksman, Pierre Duhamel
    Synthesis of hybrid filter banks by global frequency domain least square solving. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5565-5568 [Conf]
  1391. Vincenzo Ferragina, Piero Malcovati, Fausto Borghetti, A. Rossini, Franco Ferrari, Nicoletta Ratti, Giuseppe Bertuccio
    Implementation of a novel read-out strategy based on a Wilkinson ADC for a 16×16 pixel X-ray detector array. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5569-5572 [Conf]
  1392. Guo-Ming Sung, Kuo-Hsuan Chang, Wen-Sheng Lin
    A 12-B 10-msamples/s CMOS switched-current delta-sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5573-5576 [Conf]
  1393. Oguz Altun, Jinseok Koh, Phillip E. Allen
    A 1.5V multirate multibit sigma delta modulator for GSM/WCDMA in a 90 nm digital CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5577-5580 [Conf]
  1394. Francisco Colodro Ruiz, Antonio B. Torralba, Marta Laguna Garcia
    Time-interleaved multirate sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5581-5584 [Conf]
  1395. Ramon Tortosa Navas, José Manuel de la Rosa Utrera, Ángel Rodríguez-Vázquez, Francisco Vidal Fernández Fernández
    A direct synthesis method of cascaded continuous-time sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5585-5588 [Conf]
  1396. Yuan Chen, Kei-Tee Tiew
    A sixth-order subsampling continuous-time bandpass delta-sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5589-5592 [Conf]
  1397. Mohammad Yavari, Omid Shoaei
    High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5593-5596 [Conf]
  1398. Adão Antônio de Souza Jr., Luigi Carro, Jawad Tousaad
    Adaptive processing applied to the design of highly digital analog interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5597-5600 [Conf]
  1399. Maciej Borkowski, Juha Kostamovaara
    Spurious tone free digital delta-sigma modulator design for DC inputs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5601-5604 [Conf]
  1400. Slawomir Koziel, John W. Bandler, Kaj Madsen
    Towards a rigorous formulation of the space mapping technique for engineering design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5605-5608 [Conf]
  1401. Jesús Ruiz-Amaya, José Manuel de la Rosa Utrera, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
    Behavioral modeling simulation and high-level synthesis of pipeline A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5609-5612 [Conf]
  1402. Yuanzhong Wan, Maitham Shams
    Delay modeling of CMOS/CPL logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5613-5616 [Conf]
  1403. Mohammad Hekmat, Shahriar Mirabbasi, Majid Hashemi
    Ground bounce calculation due to simultaneous switching in deep sub-micron integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5617-5620 [Conf]
  1404. Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe
    Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5621-5624 [Conf]
  1405. K. Folkesson, C. Svensson, B. Knuthammar, A. Dreyfert
    A high-level dynamic-error model of a pipelined analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5625-5628 [Conf]
  1406. Hui Zhang, Preethi Karthik, Hua Tang, Alex Doboli
    An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5629-5632 [Conf]
  1407. Shih-Hsu Huang, Chun-Hua Cheng
    A formal approach to the slack driven scheduling problem in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5633-5636 [Conf]
  1408. G. Caruso
    Design of MOS current mode logic gates - computing the limits of voltage swing and bias current. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5637-5640 [Conf]
  1409. Yunfeng Wang, Jinian Bian, Xianlong Hong
    Interconnect delay optimization via high level re-synthesis after floorplanning. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5641-5644 [Conf]
  1410. Xianwu Xing, Ching-Chuen Jong
    Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5645-5648 [Conf]
  1411. Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu
    BDD decomposition for mixed CMOS/PTL logic circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5649-5652 [Conf]
  1412. Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang
    FPGA technology mapping optimization by rewiring algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5653-5656 [Conf]
  1413. Michael Walter Payton, Fat Duen Ho
    A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5657-5661 [Conf]
  1414. Luo Chun, Yang Jun, Gao Gugang, Shi Longxing
    Domain fault model and coverage metric for SoC verification. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5662-5665 [Conf]
  1415. Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen
    Validation analysis and test flow optimization of VLSI chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5666-5669 [Conf]
  1416. Ji Li, Yinhe Han, Xiaowei Li
    Deterministic and low power BIST based on scan slice overlapping. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5670-5673 [Conf]
  1417. Tsung-Hsi Chiang, Lan-Rong Dung, Ming-Feng Yaung
    Modeling and formal verification of dataflow graph in system-level design using Petri net. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5674-5677 [Conf]
  1418. Tan Yan, Haruna Murata
    A robust and correct computation for the curvilinear routing problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5678-5681 [Conf]
  1419. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing Ya Jou
    Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5682-5685 [Conf]
  1420. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-based delay fault self-testing of pipelined processor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5686-5689 [Conf]
  1421. Sanqing Hu, Derong Liu, Huaguang Zhang
    Gradient-based methods for simultaneous blind separation of mixed source signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5690-5693 [Conf]
  1422. Kuniharu Kishida
    Blind identification of brain mechanism in MEG. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5694-5697 [Conf]
  1423. Bao-Yun Wang, Wei Xing Zheng
    Chaotic signal separation from a linear mixture. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5698-5701 [Conf]
  1424. Ching-An Lin, Yi-Sheng Chen
    Blind identification of MIMO channels with periodic modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5702-5705 [Conf]
  1425. Yiwen Zhang, Qinye Yin, Le Ding, Ronghai Sun
    Blind low rate multiuser detection for multirate multicarrier CDMA systems using antenna array. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5706-5709 [Conf]
  1426. Yanxing Zeng, Qinye Yin, Le Ding, Yinkuo Meng, Ying Zhang
    DOA-matrix decoder for STBC-MC-CDMA systems over frequency-selective channel. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5710-5713 [Conf]
  1427. E. Principi, Stefano Squartini, Francesco Piazza
    An ICA based approach for blind deconvolution of three-dimensional signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5714-5717 [Conf]
  1428. Yun Ye, Saman S. Abeysekera
    Evaluating a blind channel estimation technique that uses a hardware efficient equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5718-5721 [Conf]
  1429. Noriyuki Hirai, Hiroki Matsumoto, Toshihiro Furukawa, Kiyoshi Furuya
    A consideration of blind source separation using wavelet transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5722-5725 [Conf]
  1430. Nuo Zhang, Xiaowei Zhang, Jianming Lu, Takashi Yahagi
    An approach for nonlinear blind source separation of signals with noise using neural networks and higher-order cumulants. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5726-5729 [Conf]
  1431. Amir Minayi Jalil, Hamidreza Amindavar, Farshad Almasganj
    Subband blind equalization using wavelet filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5730-5733 [Conf]
  1432. M. Khademul Islam Molla, Keikichi Hirose, Nobuaki Minematsu
    Audio source separation by source localization with Hilbert spectrum. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5734-5737 [Conf]
  1433. Ke Deng, Qinye Yin, Hongbo Tian
    Uplink channel estimation for space-time block coded multiple-input multiple-output MC-CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5738-5741 [Conf]
  1434. Massimo Tomassoni, Stefano Squartini, Francesco Piazza
    An alternative natural gradient approach for multichannel blind deconvolution. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5742-5745 [Conf]
  1435. Izzet Ozcelik, Izzet Kale, Buyurman Baykal
    Decision feedback equalizer with the blind matched filter estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5746-5749 [Conf]
  1436. Foster F. Dai, Shengfang Wei, Richard D. Jaeger
    Integrated blind electronic equalizer for fiber dispersion compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5750-5753 [Conf]
  1437. Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero
    Linear and nonlinear macromodels for power/signal integrity. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5754-5757 [Conf]
  1438. Rohan Mandrekar, Madhavan Swaminathan
    Delay extraction from frequency domain data for causal macro-modeling of passive networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5758-5761 [Conf]
  1439. Yuichi Tanji, Hidemasa Kubota
    Passive approximation of tabulated frequency-data by Fourier expansion method. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5762-5765 [Conf]
  1440. Joungho Kim, Junso Pak, Jongbae Park, Hyungsoo Kim
    Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5766-5769 [Conf]
  1441. Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla
    Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5770-5773 [Conf]
  1442. Takayuki Watanabe, Hideki Asai
    Modeling of power distribution networks with signal lines for SPICE simulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5774-5777 [Conf]
  1443. In-Cheol Park, Se-Hyeon Kang
    Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5778-5781 [Conf]
  1444. Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
    Quantized LDPC decoder design for binary symmetric channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5782-5785 [Conf]
  1445. Zhongfeng Wang, Qing-wei Jia
    Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5786-5789 [Conf]
  1446. David Haley, Chris Winstead, Vincent C. Gaudet, Alex J. Grant, Christian Schlegel
    An analog/digital mode-switching LDPC codec. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5790-5793 [Conf]
  1447. Wei-Hsiang Tseng, Ching-Chi Chang, Chorng-Kuang Wang
    Digital VLSI OFDM transceiver architecture for wireless SoC design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5794-5797 [Conf]
  1448. Victor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello
    A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5798-5801 [Conf]
  1449. Ákos Zarándy, Péter Földesy, Péter Szolgay, Szabolcs Tõkés, Csaba Rekeczky, Tamás Roska
    Various implementations of topographic, sensory, cellular wave computers. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5802-5805 [Conf]
  1450. Piotr Dudek
    Implementation of SIMD vision chip with 128×128 array of analogue processing elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5806-5809 [Conf]
  1451. Mika Laiho, Ari Paasio
    Dynamically coupled multi-layer mixed-mode CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5810-5813 [Conf]
  1452. Mustak E. Yalcin, Johan A. K. Suykens, Joos Vandewalle
    Spatiotemporal pattern formation in the ACE16k CNN chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5814-5817 [Conf]
  1453. Paolo Arena, Luigi Fortuna, Mattia Frasca, Guido Vagliasindi, Adriano Basile
    CNN wave based computation for robot navigation on ACE16K. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5818-5821 [Conf]
  1454. Charoensak Charayaphan, Farook Sattar
    A single-chip FPGA design for real-time ICA-based blind source separation algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5822-5825 [Conf]
  1455. Isa Servan Uzun, Abbes Amira
    Design and FPGA implementation of finite Ridgelet transform [image processing applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5826-5829 [Conf]
  1456. Byonghyo Shim, Hyung G. Myung
    A novel metric representation for low-complexity log-MAP decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5830-5833 [Conf]
  1457. Leticia V. Guimaraes, André Soares, Viviane Cordeiro, Altamiro Amadeu Susin
    Gradient pile up for edge detection on hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5834-5837 [Conf]
  1458. Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu
    Area-efficient systolic architectures for inversions over GF(2/sup m/). [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5838-5841 [Conf]
  1459. Wei Han, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
    A speech recognizer with selectable model parameters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5842-5845 [Conf]
  1460. Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma
    Reconfigurable multiple scan-chains for reducing test application time of SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5846-5849 [Conf]
  1461. Wang Zhong-hai, Ye Yi-zheng
    The improvement for transaction level verification functional coverage. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5850-5853 [Conf]
  1462. Ju Yeob Kim, Sung Je Hong, Jong Kim
    Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5854-5857 [Conf]
  1463. B. Afkal, Ali Afzali-Kusha, Mahmoud El Nokali
    Efficient power model for crossbar interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5858-5861 [Conf]
  1464. Rung-Bin Lin
    Coupling reduction analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5862-5865 [Conf]
  1465. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Energy and latency evaluation of NoC topologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5866-5869 [Conf]
  1466. Kiyotaka Kohno, Yujiro Inouye, Mitsuru Kawamoto
    An adaptive super-exponential deflation algorithm for blind deconvolution of MIMO systems using the matrix pseudo-inversion lemma. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5870-5873 [Conf]
  1467. Hyung-Min Park, Chandra Shekhar Dhir, Do-Kwan Oh, Soo-Young Lee
    Filterbank-based blind signal separation with estimated sound direction. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5874-5877 [Conf]
  1468. Fabian J. Theis
    Blind signal separation into groups of dependent signals using joint block diagonalization. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5878-5881 [Conf]
  1469. H. Sawada, S. Araki, R. Mukai, S. Makino
    Blind extraction of a dominant source from mixtures of many sources using ICA and time-frequency masking. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5882-5885 [Conf]
  1470. Sookjeong Kim, Seungjin Choi
    Independent arrays or independent time courses for gene expression time series. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5886-5889 [Conf]
  1471. Jan Eriksson, Visa Koivunen
    Blind separation of a class of nonlinear ICA models. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5890-5893 [Conf]
  1472. Jichuan Zhao, Ahmet T. Erdogan, Tughrul Arslan
    A novel application specific network protocol for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5894-5897 [Conf]
  1473. Devrim Yilmaz Aksin, Stefano Gregori, Franco Maloberti
    High-efficiency power amplifier for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5898-5901 [Conf]
  1474. Nicola Viarani, Nicola Massari, Massimo Gottardi
    A new switched capacitor circuit for parallel-pixel image processing [vision sensor integrated signal processing]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5902-5905 [Conf]
  1475. Youngbok Kim, Anuj Agarwal, Sameer R. Sonkusale
    Broadband dielectric spectroscopy CMOS readout circuit for molecular sensing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5906-5909 [Conf]
  1476. Salvatore Baglio, Vincenzo Sacco, Adi R. Bulsara
    Read-out circuit in RT-fluxgate. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5910-5913 [Conf]
  1477. Carina K. Leung, Denise M. Wilson
    Integrated interface circuits for chemiresistor arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5914-5917 [Conf]
  1478. Tetsuro Fujii, Kazuhiro Shirakawa, Mitsuru Nomura, Takahiro Yamaguchi
    SHD movie distribution system using image container with 4096×2160 pixel resolution and 36 bit color. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5918-5921 [Conf]
  1479. Junichi Hara
    An implementation of JPEG 2000 interactive image communication system. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5922-5925 [Conf]
  1480. Noriaki Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, Takashi Akazawa
    Designing and packaging technology of Renesas SIP. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5926-5929 [Conf]
  1481. Kazutoshi Wakabayashi
    System LSI design with C-based behavioral synthesis and verification. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5930-5933 [Conf]
  1482. Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki
    Approach for physical design in sub-100 nm era. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5934-5937 [Conf]
  1483. Nobuyuki Nishiguchi
    An advance RTL to GDS2 design methodology for 90 nm and below system LSIs to solve timing closure, signal integrity and design for manufacturing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5938-5941 [Conf]
  1484. Shengyuan Li, Susanta Sengupta, Huseyin Dinc, Phillip E. Allen
    CMOS high-linear wide-dynamic range RF on-chip filters using Q-enhanced LC filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5942-5945 [Conf]
  1485. Muhammad S. Qureshi, Phillip E. Allen
    70 MHz CMOS gm-C IF filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5946-5949 [Conf]
  1486. Chun-Ming Chang
    Voltage-mode high-order OTA-only-without-C low-pass (from 215 M to 705 M Hz) and band-pass (from 214 M to 724 M Hz) filter structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5950-5953 [Conf]
  1487. Phanumas Khumsat, Apisak Worapishet
    Application of reverse-active npns for compact, wide-tuning f/sub T/-integration-based filters in SiGe HBT BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5954-5957 [Conf]
  1488. Masood ul-Hasan, Yichuang Sun
    A 2 V 0.25µm CMOS 250 MHz fully-differential seventh-order equiripple linear phase LF filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5958-5961 [Conf]
  1489. Shanthi Pavan, Shankar Shivappa
    Analysis of traveling wave and transversal analog adaptive equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5962-5965 [Conf]
  1490. Phil Corbishley, David G. Haigh
    Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5966-5969 [Conf]
  1491. Somsak Akatimagool
    Fast iterative method package for high frequency circuits analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5970-5973 [Conf]
  1492. Tuna B. Tarim
    Mixed signal and SoC design flow requirements. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5974-5977 [Conf]
  1493. Raoul F. Badaoui, Ranga Vemuri
    Analog VLSI circuit-level synthesis using multi-placement structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5978-5981 [Conf]
  1494. Andrea Fornasari, Piero Malcovati, Franco Maloberti
    Improved modeling of sigma-delta modulator non-idealities in Simulink. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5982-5985 [Conf]
  1495. Volodymyr Kratyuk, Igor Vytyaz, Un-Ku Moon, Kartikeya Mayaram
    Analysis of supply and ground noise sensitivity in ring and LC oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5986-5989 [Conf]
  1496. Yodchanan Wongsawat, K. R. Rao, Soontorn Oraintara
    Multichannel SVD-based image de-noising. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5990-5993 [Conf]
  1497. Woon S. Gan, Sen M. Kuo
    Analysis of nonlinear residual echo suppressors for telecommunications [voice communication applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5994-5997 [Conf]
  1498. Li Guo, Yih-Fang Huang
    SMF robust filtering in impulsive noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5998-6001 [Conf]
  1499. Chien-Hsun Tseng, Stuart Lawson
    Modelling of high-order mechanical plate vibration systems by multidimensional wave digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6002-6005 [Conf]
  1500. Hsiang-Feng Chi, Zhao-Hong Lai
    A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wire-line transmission systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6006-6009 [Conf]
  1501. Charles W. Therrien
    Defining correlation functions and power spectra for multirate random processes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6010-6013 [Conf]
  1502. Shinji Hosokawa, Shuichi Ohno, Kok ann Donny Teo, Takao Hinamoto
    Pilot tone design for peak-to-average power ratio reduction in OFDM. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6014-6017 [Conf]
  1503. Zhiyong He, Sébastien Roy, Paul Fortier
    High-speed and low-power design of parallel turbo decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6018-6021 [Conf]
  1504. Huaizhong Lin, Bo Zhou, Zengwei Zheng, Chun Chen
    Efficient view maintenance in wireless networks [mobile database view maintenance applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6022-6025 [Conf]
  1505. Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu
    Digital signal processing engine design for polar transmitter in wireless communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6026-6029 [Conf]
  1506. Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu, Chen-Yi Lee
    A novel technique for I/Q imbalance and CFO compensation in OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6030-6033 [Conf]
  1507. Sankaran Aniruddhan, David J. Allstot
    Architectural issues in base-station frequency synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6034-6037 [Conf]
  1508. Guo-Ping Jiang, Wei Xing Zheng, Wallace Kit-Sang Tang, Guanrong Chen
    Integral observer approach for chaos synchronization with transmission disturbances. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6038-6041 [Conf]
  1509. Cheng Shen, Zhiguo Shi, Lixin Ran
    Synchronizing chaotic Colpitts circuits adaptively with parameter mismatches and channel distortions. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6042-6045 [Conf]
  1510. Chai Wah Wu
    Synchronization in an array of chaotic systems coupled via a directed graph. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6046-6049 [Conf]
  1511. Yue Ma, Hiroshi Kawakami, Chi K. Michael Tse, Takuji Kousaka
    A subtle link in switched dynamical systems: saddle-node bifurcation meets border collision. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6050-6053 [Conf]
  1512. Takuya Yoshimura, Kuniyasu Shimizu, Tetsuro Endo
    Bifurcation and transitional dynamics in asymmetrical two-coupled oscillators with hard type nonlinearity. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6054-6057 [Conf]
  1513. Shigeki Tsuji, Tetsushi Ueta, Hiroshi Kawakami, Kazuyuki Aihara
    Bifurcations in modified BVP neurons connected by inhibitory and electrical coupling. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6058-6061 [Conf]
  1514. Tamer Shanableh, Tony May
    Error sensitivity testing for the MC-EZBC scalable wavelet video coder. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6062-6065 [Conf]
  1515. Ya-Hui Yu, Chun-Jen Tsai
    A model-based rate allocation mechanism for wavelet-based embedded image and video coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6066-6069 [Conf]
  1516. Tao Fang, Lap-Pui Chau
    Optimal resynchronization for layered video over wireless channel. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6070-6073 [Conf]
  1517. Dong Tian, Miska M. Hannuksela, Moncef Gabbouj
    Sub-sequence video coding for improved temporal scalability. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6074-6077 [Conf]
  1518. Wenxian Yang, Feng Wu, Yan Lu, Jianfei Cai, King Ngi Ngan, Shipeng Li
    Scalable multiview video coding using wavelet. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6078-6081 [Conf]
  1519. Li-Fu Ding, Shao-Yi Chien, Yu-Wen Huang, Yu-Lin Chang, Liang-Gee Chen
    Stereo video coding system with hybrid coding based on joint prediction scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6082-6085 [Conf]
  1520. Ka-yau Ho, Shu-hung Leung
    A generalized semi-blind channel estimation for pilot-aided OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6086-6089 [Conf]
  1521. Jan H. Rutger Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta
    Jitter limitations on multi-carrier modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6090-6093 [Conf]
  1522. Visa Koivunen, Mihai Enescu
    Estimating the fading coefficient in mobile OFDM systems using state-space model. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6094-6097 [Conf]
  1523. Yin-Tsung Hwang, Chen-Yu Tsai, Cheng-Chen Lin
    Block-wise adaptive modulation for OFDM WLAN systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6098-6101 [Conf]
  1524. M. Ma, E. Masoud, Y. Sun, John M. Senior
    A hybrid space-time and collaborative coding scheme for wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6102-6105 [Conf]
  1525. Ravi Chawla, Christopher M. Twigg, Paul E. Hasler
    An analog modulator/demodulator using a programmable arbitrary waveform generator. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6106-6109 [Conf]
  1526. Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo
    A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6110-6113 [Conf]
  1527. Saku Hamalainen, Lauri Koskinen, Kari Halonen
    A hardware-based predictive motion estimation algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6114-6117 [Conf]
  1528. Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma
    A multiplication-accumulation computation unit with optimized compressors and minimized switching activities. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6118-6121 [Conf]
  1529. Wen-Kai Huang, I-Ting Lin, Shi-Wei Chen, Ing-Jer Huang
    A cost-effective media processor for embedded applications [audio decoder example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6122-6125 [Conf]
  1530. Jui-Cheng Yen, Hun-Chen Chen, Shu-Meng Wu
    Design and implementation of a new cryptographic system for multimedia transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6126-6129 [Conf]
  1531. Sebastián López, Gustavo Marrero Callicó, José Francisco López, Roberto Sarmiento, Antonio Núñez
    Low-cost implementation of a super-resolution algorithm for real-time video applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6130-6133 [Conf]
  1532. Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
    A 0.35µm CMOS comparator circuit for high-speed ADC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6134-6137 [Conf]
  1533. Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
    A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6138-6141 [Conf]
  1534. Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen
    A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6142-6145 [Conf]
  1535. Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire
    A 1.2 GHz adaptive floating gate comparator with 13-bit resolution. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6146-6149 [Conf]
  1536. Hamid Movahedian, Meysam Azin, Mehrdad Sharif Bakhtiar
    An 8-bit 160 MS/s folding-interpolating ADC with optimized active averaging/interpolating network. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6150-6153 [Conf]
  1537. Philomena C. Brady, Paul E. Hasler
    Offset compensation in flash ADCs using floating-gate circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6154-6157 [Conf]
  1538. Dinh Hung Dang, Yvon Savaria, Mohamad Sawan
    A novel approach for implementing ultra-high speed flash ADC using MCML circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6158-6161 [Conf]
  1539. Martijn F. Snoeij, Albert J. P. Theuwissen, Johan H. Huijsing
    A 1.8 V 3.2µW comparator for use in a CMOS imager column-level single-slope ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6162-6165 [Conf]
  1540. Johan Piper, Jiren Yuan
    Design considerations of a floating-point ADC with embedded S/H. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6166-6169 [Conf]
  1541. Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen
    A new CCII-based pipelined analog to digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6170-6173 [Conf]
  1542. Q. Wu, A. Wang
    A 12 bits/200 MHz resolution/sampling/power-optimized ADC in 0.25µm SiGe BiCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6174-6177 [Conf]
  1543. SeongHwan Cho, Sungmin Ock, Sang-Hoon Lee, Joon-Suk Lee
    A low power pipelined analog-to-digital converter using series sampling capacitors. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6178-6181 [Conf]
  1544. Vivek Sharma, Un-Ku Moon, Gabor C. Temes
    A generic multilevel multiplying D/A converter for pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6182-6185 [Conf]
  1545. Thirumalai Rengachari, Vivek Sharma, Gabor C. Temes, Un-Ku Moon
    A 10-bit algorithmic A/D converter for cytosensor application. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6186-6189 [Conf]
  1546. Degang Chen, Zhongjun Yu, Randall L. Geiger
    An adaptive, truly background calibration method for high speed pipeline ADC design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6190-6193 [Conf]
  1547. Shigeto Tanaka, Yuji Ghoda, Yasuhiro Sugimoto
    The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6194-6197 [Conf]
  1548. Mohammad S. Sharawi, Daniel N. Aloi
    An 800 Mbps system interconnect modeling and simulation for high speed computing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6198-6201 [Conf]
  1549. Bogdan J. Falkowski, Shixing Yan
    Ternary Walsh transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6202-6205 [Conf]
  1550. Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga
    A post layout watermarking method for IP protection. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6206-6209 [Conf]
  1551. Masayuki Masuda, Kazuhito Ito
    Rapid and precise instruction set evaluation for application specific processor design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6210-6213 [Conf]
  1552. Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang, Hsin-Hsien Ho
    Modem floorplanning with abutment and fixed-outline constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6214-6217 [Conf]
  1553. Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Amelifard, Ali Afzali-Kusha
    Modeling of MOS transistors based on genetic algorithm and simulated annealing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6218-6221 [Conf]
  1554. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
    VLSI block placement with alignment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6222-6225 [Conf]
  1555. Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali
    Multiobjective VLSI cell placement using distributed simulated evolution algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6226-6229 [Conf]
  1556. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
    A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6230-6233 [Conf]
  1557. Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang
    A new congestion and crosstalk aware router. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6234-6237 [Conf]
  1558. Laleh Behjat, Andy Chiang
    Fast integer linear programming based models for VLSI global routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6238-6243 [Conf]
  1559. Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
    Floorplanning with clock tree estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6244-6247 [Conf]
  1560. Fei He, William N. N. Hung, Xiaoyu Song, Ming Gu, Jiaguang Sun
    Segmented channel routing with pin rearrangements via satisfiability. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6248-6251 [Conf]
  1561. Abbes Amira, Peter Farrell
    An automatic face recognition system based on wavelet transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6252-6255 [Conf]
  1562. Yukinori Nagase, Takahiko Yamamoto, Takao Kawamura, Kazunori Sugahara
    Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6256-6259 [Conf]
  1563. Tai-Wai Chan, Oscar C. Au, Tak-Song Chong, Wing-San Chau
    A novel content-adaptive interpolation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6260-6263 [Conf]
  1564. Shuai Yuan, Akira Taguchi, Masayuki Kawamata
    Arbitrary scale image enlargement with the prediction of high frequency components. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6264-6267 [Conf]
  1565. T. Kobayashi, T. Shimamura, T. Hosoya, Y. Takahashi
    Restoration from image degraded by white noise based on iterative spectral subtraction method. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6268-6271 [Conf]
  1566. Kati Virtanen, N. Pankaala, Ari Paasio
    Compensation of errors generated by an analog 2D DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6272-6275 [Conf]
  1567. Guoping Qiu, Jiang Duan
    An optimal tone reproduction curve operator for the display of high dynamic range images. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6276-6279 [Conf]
  1568. Yuichi Kida, Takuro Kida
    The FIR filter bank with given analysis filters that minimizes various worst-case measures of error at the same time. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6280-6283 [Conf]
  1569. Hung-An Chang, Homer Chen
    Directionally weighted color interpolation for digital cameras. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6284-6287 [Conf]
  1570. Jhing-Fa Wang, Chien-Shun Wang, Han-Jen Hsu
    A novel color interpolation algorithm by pre-estimating minimum square error. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6288-6291 [Conf]
  1571. Noritaka Yamashita, Munenori Ogura, Jianming Lu, Hiroo Sekiya, Takashi Yahagi
    A random-valued impulse noise detector using level detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6292-6295 [Conf]
  1572. Andy C. Yau, N. K. Bose, Michael K. Ng
    Super-resolution image restoration from blurred observations. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6296-6299 [Conf]
  1573. Wei-Chih Shen, Ruey-Feng Chang
    A nearest neighbor graph based watershed algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6300-6303 [Conf]
  1574. Bin B. Zhu, Shipeng Li, Yang Yang
    JPEG 2000 encryption enabling fine granularity scalability without decryption. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6304-6307 [Conf]
  1575. Kohei Inoue, Kiichi Urahama
    DSVD: a tensor-based image compression and recognition method. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6308-6311 [Conf]
  1576. Yue-xin Zhu, Nan-Ning Zheng, Jing Zhang, Zong-ze Wu
    Approximate treatment for calculation of the rate-distortion slope in EBCOT. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6312-6315 [Conf]
  1577. Xing Qin, Xiaolang Yan, Haitong Ge, Ye Yang
    A simplified algorithm of JPEG2000 rate control for VLSI implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6316-6319 [Conf]
  1578. Megumi Takezawa, Hirofumi Sanada, Kazuhisa Watanabe, Miki Haseyama
    Quality improvement technique for JPEG images with fractal image coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6320-6323 [Conf]
  1579. Osamu Watanabe, Akiko Nakazaki, Hitoshi Kiya
    A scalable encryption method allowing backward compatibility with JPEG2000 images. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6324-6327 [Conf]
  1580. Takuma Ishida, Shogo Muramatsu, Hisakazu Kikuchi
    Lossless implementation of Motion JPEG2000 integrated with invertible deinterlacing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6328-6331 [Conf]
  1581. Zhibin Pan, Koji Kotani, Tadahiro Ohmi
    Improved fast encoding method for vector quantization based on subvector technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6332-6335 [Conf]
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