Conferences in DBLP
Enhancing industry participation in ISCAS and Circuits and Systems Society. [Citation Graph (, )][DBLP ] Design of an ultra-low power SA-ADC with medium/high resolution and speed. [Citation Graph (, )][DBLP ] A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. [Citation Graph (, )][DBLP ] A 52mW 0.56mm^{2} 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration. [Citation Graph (, )][DBLP ] A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS. [Citation Graph (, )][DBLP ] General analysis on the impact of phase-skew in time-interleaved ADCs. [Citation Graph (, )][DBLP ] A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. [Citation Graph (, )][DBLP ] HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV. [Citation Graph (, )][DBLP ] Frame-parallel design strategy for high definition B-frame H.264/AVC encoder. [Citation Graph (, )][DBLP ] Prediction-based real-time CABAC decoder for high definition H.264/AVC. [Citation Graph (, )][DBLP ] A HW CABAC encoder with efficient context access scheme for H.264/AVC. [Citation Graph (, )][DBLP ] New narrowband active noise control systems with significantly less computational requirements. [Citation Graph (, )][DBLP ] Minimum redundancy MIMO radars. [Citation Graph (, )][DBLP ] Sliding window online Kernel-based classification by projection mappings. [Citation Graph (, )][DBLP ] Semi-blind data-selective algorithms for channel equalization. [Citation Graph (, )][DBLP ] Fixed-point analysis of adaptive filters based on the EDS algorithm. [Citation Graph (, )][DBLP ] BW extension in shunt feedback transimpedance amplifiers using negative miller capacitance. [Citation Graph (, )][DBLP ] Tunable transimpedance amplifiers with constant bandwidth for optical communications. [Citation Graph (, )][DBLP ] A simple class-AB transconductor in CMOS. [Citation Graph (, )][DBLP ] A -72 dB @ 2 MHz IM3 CMOS tunable pseudo-differential transconductor. [Citation Graph (, )][DBLP ] Bulk-driven gain-enhanced fully-differential amplifier for VT + 2Vdsat operation. [Citation Graph (, )][DBLP ] Coefficient decimation approach for realizing reconfigurable finite impulse response filters. [Citation Graph (, )][DBLP ] A reconfigurable multi-stage frequency response masking filter bank architecture for software defined radio receivers. [Citation Graph (, )][DBLP ] Concept for an adaptive digital front-end for multi-mode wireless receivers. [Citation Graph (, )][DBLP ] Filter bank based frequency-domain equalizers with diversity combining. [Citation Graph (, )][DBLP ] Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. [Citation Graph (, )][DBLP ] Network topology estimation through synchronization: A case study on quantum dot CNN. [Citation Graph (, )][DBLP ] Solving ability of Hopfield Neural Network with scale-rule noise for QAP. [Citation Graph (, )][DBLP ] Topology identification of an uncertain general complex dynamical network. [Citation Graph (, )][DBLP ] Wave propagation in oscillators coupled by time-varying resistor with timing mismatch. [Citation Graph (, )][DBLP ] Constraint modules: An introduction. [Citation Graph (, )][DBLP ] Recently developed approaches for solving blind deconvolution of MIMO-IIR Systems: Super-exponential and eigenvector methods. [Citation Graph (, )][DBLP ] Semi-blind channel estimation of MIMO-OFDM systems with pulse shaping. [Citation Graph (, )][DBLP ] Perturbation analysis of subspace-based semi-blind MIMO channel estimation approaches. [Citation Graph (, )][DBLP ] Blind identification of MIMO channels with periodic precoders. [Citation Graph (, )][DBLP ] Blind block synchronization algorithms in cyclic prefix systems. [Citation Graph (, )][DBLP ] Power-delay optimization in MCML tapered buffers. [Citation Graph (, )][DBLP ] Improving the power-delay product in SCL circuits using source follower output stage. [Citation Graph (, )][DBLP ] An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. [Citation Graph (, )][DBLP ] Transistor-level programmable MOS analog IC with body biasing. [Citation Graph (, )][DBLP ] High speed serial interface for mobile LCD driver IC. [Citation Graph (, )][DBLP ] A two-stator MEMS power generator for cardiac pacemakers. [Citation Graph (, )][DBLP ] A fully differential CMOS capacitance sensor design, testing and array architecture. [Citation Graph (, )][DBLP ] Graphene nanoribbon field-effect transistors. [Citation Graph (, )][DBLP ] Analyzing mixed carbon nanotube bundles: A current density study. [Citation Graph (, )][DBLP ] Carbon nanotube circuit design choices in the presence of metallic tubes. [Citation Graph (, )][DBLP ] Bilateral design of mm-wave LNA and receiver front-end in 90nm CMOS. [Citation Graph (, )][DBLP ] A 700Mbit/s CMOS capacitive feedback front-end amplifier with automatic gain control for broadband optical wireless links. [Citation Graph (, )][DBLP ] 124dB.Hz^{2/3} Dynamic range transimpedance amplifier for electronic-photonic channelizer. [Citation Graph (, )][DBLP ] A 10 Gb/s optical receiver in 0.25 µm silicon-on-sapphire CMOS. [Citation Graph (, )][DBLP ] An optically powered, free space optical communications receiver. [Citation Graph (, )][DBLP ] Minimum energy broadcasting in wireless networks (extended abstract). [Citation Graph (, )][DBLP ] Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs. [Citation Graph (, )][DBLP ] A method for verifying deadlock freedom and liveness of petri nets. [Citation Graph (, )][DBLP ] On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract). [Citation Graph (, )][DBLP ] Versatile graphs for tail-biting convolutional codes. [Citation Graph (, )][DBLP ] Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC. [Citation Graph (, )][DBLP ] A 10-bit 8.3MS/s switched-current successive approximation ADC for column-parallel imagers. [Citation Graph (, )][DBLP ] Predictive timing error calibration technique for RF current-steering DACs. [Citation Graph (, )][DBLP ] New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise. [Citation Graph (, )][DBLP ] Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. [Citation Graph (, )][DBLP ] Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. [Citation Graph (, )][DBLP ] A fault-tolerant, DFA-resistant AES core. [Citation Graph (, )][DBLP ] Modeling and exploration of a reconfigurable architecture for digital holographic imaging. [Citation Graph (, )][DBLP ] Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems. [Citation Graph (, )][DBLP ] A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. [Citation Graph (, )][DBLP ] Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression. [Citation Graph (, )][DBLP ] Multiframe image super-resolution using quasi-newton algorithms. [Citation Graph (, )][DBLP ] Application of scalable visual sensitivity profile in image and video coding. [Citation Graph (, )][DBLP ] Modeling of the DCT coefficients of images. [Citation Graph (, )][DBLP ] Target region-aware tone reproduction. [Citation Graph (, )][DBLP ] A 1.5 bit 5^{th} order CT/DT delta sigma class D amplifier with power efficiency improvement. [Citation Graph (, )][DBLP ] PSRR of bridge-tied load PWM Class D Amps. [Citation Graph (, )][DBLP ] High slew rate two stage A/AB and AB/AB op-amps with phase lead compensation at output node and local common mode feedback. [Citation Graph (, )][DBLP ] A simple approach for the implementation of CMOS amplifiers with constant bandwidth independent of gain. [Citation Graph (, )][DBLP ] A novel topology in RNMC amplifiers with single miller compensation capacitor. [Citation Graph (, )][DBLP ] VLSI architecture for data-reduced steering matrix feedback in MIMO systems. [Citation Graph (, )][DBLP ] Hardware-efficient steering matrix computation architecture for MIMO communication systems. [Citation Graph (, )][DBLP ] A single-FPGA multipath MIMO fading channel simulator. [Citation Graph (, )][DBLP ] A modified MMSE-SD soft detector for coded MIMO-OFDM systems. [Citation Graph (, )][DBLP ] The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection. [Citation Graph (, )][DBLP ] Introducing Complex Oscillation Based Test: an application example targeting Analog to Digital Converters. [Citation Graph (, )][DBLP ] Stability study of the TCP-RED system using detrended fluctuation analysis. [Citation Graph (, )][DBLP ] Rotation map with a controlling segment and its application to A/D converters. [Citation Graph (, )][DBLP ] A quantum-dot light-harvesting architecture using deterministic phase control. [Citation Graph (, )][DBLP ] A method based on a genetic algorithm to find PWL approximations of multivariate nonlinear functions. [Citation Graph (, )][DBLP ] General-pupose technology for a general-purpose nervous system. [Citation Graph (, )][DBLP ] Pulse-based signal compression for implanted neural recording systems. [Citation Graph (, )][DBLP ] Radios for the brain? a practical micropower sensing and algorithm architecture for neurostimulators. [Citation Graph (, )][DBLP ] Implant electronics for intraocular epiretinal neuro-stimulators. [Citation Graph (, )][DBLP ] Stimulation and recording of neural tissue, closing the loop on the artifact. [Citation Graph (, )][DBLP ] Power-aware topology optimization for networks-on-chips. [Citation Graph (, )][DBLP ] Design target exploration for meeting time-to-market using pareto analysis. [Citation Graph (, )][DBLP ] A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design. [Citation Graph (, )][DBLP ] A robust alternate repeater technique for high performance busses in the multi-core era. [Citation Graph (, )][DBLP ] Input port reduction for efficient substrate extraction in large scale IC's. [Citation Graph (, )][DBLP ] Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. [Citation Graph (, )][DBLP ] Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. [Citation Graph (, )][DBLP ] Low variation current source for 90nm CMOS. [Citation Graph (, )][DBLP ] Design of process variation tolerant radio frequency low noise amplifier. [Citation Graph (, )][DBLP ] Binary translation process to optimize nanowire arrays usage. [Citation Graph (, )][DBLP ] Cross-dimensional quality assessment for low bitrate video. [Citation Graph (, )][DBLP ] Backward-forward distortion minimization for binary images data hiding. [Citation Graph (, )][DBLP ] Peceptual distortion metric based on wavelet frequency sensitivity and multiple visual fixations. [Citation Graph (, )][DBLP ] Adaptive feature selection for digital camera source identification. [Citation Graph (, )][DBLP ] On the quality assessment of sound signals. [Citation Graph (, )][DBLP ] A two-neuron cross-correlation circuit with a wide and continuous range of time delay. [Citation Graph (, )][DBLP ] Fall detection using an address-event temporal contrast vision sensor. [Citation Graph (, )][DBLP ] Bifurcations in a silicon neuron. [Citation Graph (, )][DBLP ] A biophysically based dendrite model using programmable floating-gate devices. [Citation Graph (, )][DBLP ] The time derivative neuron. [Citation Graph (, )][DBLP ] Quadrature generation techniques for frequency multiplication based oscillators. [Citation Graph (, )][DBLP ] Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range. [Citation Graph (, )][DBLP ] A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit. [Citation Graph (, )][DBLP ] A charge-pump based 0.35µm CMOS RF switch driver for multi-standard operations. [Citation Graph (, )][DBLP ] Low-voltage bulk-driven mixer with on-chip balun. [Citation Graph (, )][DBLP ] A 65nm 10GHz pipelined MAC structure. [Citation Graph (, )][DBLP ] A new look-up table-based multiplier/squarer design for cryptosystems over GF(2^{m} ). [Citation Graph (, )][DBLP ] An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. [Citation Graph (, )][DBLP ] A high performance floating-point special function unit using constrained piecewise quadratic approximation. [Citation Graph (, )][DBLP ] Novel VLSI implementation of Peano-Hilbert curve address generator. [Citation Graph (, )][DBLP ] The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. [Citation Graph (, )][DBLP ] A novel CAVLC architecture for H.264 Video encoding at high bit-rate. [Citation Graph (, )][DBLP ] Analysis of video filtering on the cell processor. [Citation Graph (, )][DBLP ] Efficient intra-4×4 mode decision based on bit-rate estimation in H.264/AVC. [Citation Graph (, )][DBLP ] Bit-depth expansion by adaptive filter. [Citation Graph (, )][DBLP ] Automated conversion of Simulink designs to analog hardware on an FPAA. [Citation Graph (, )][DBLP ] A novel approach for automated model generation. [Citation Graph (, )][DBLP ] Accurate and reusable macromodeling technique using a fuzzy-logic approach. [Citation Graph (, )][DBLP ] Reducing the effects of component mismatch by using relative size information. [Citation Graph (, )][DBLP ] Capacitance ratio approximation in SC filters via genetic algorithm. [Citation Graph (, )][DBLP ] VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. [Citation Graph (, )][DBLP ] Enhanced delta-based layered decoding of WiMAX QC-LDPC codes. [Citation Graph (, )][DBLP ] Switching activity reducing layered decoding algorithm for LDPC codes. [Citation Graph (, )][DBLP ] A dual-core programmable decoder for LDPC convolutional codes. [Citation Graph (, )][DBLP ] Adaptive quantization in min-sum based irregular LDPC decoder. [Citation Graph (, )][DBLP ] State discontinuity analysis of linear switched systems via energy function optimization. [Citation Graph (, )][DBLP ] Injection locking conditions under small periodic excitations. [Citation Graph (, )][DBLP ] Linear probability feedback processes. [Citation Graph (, )][DBLP ] A comparative study of the new LQ-MCS control on an automotive electro-mechanical system. [Citation Graph (, )][DBLP ] Stability analysis and control of bifurcations of parallel connected DC/DC converters using the monodromy matrix. [Citation Graph (, )][DBLP ] Digitally enhanced analog circuits: System aspects. [Citation Graph (, )][DBLP ] Performance enhancement of linear power amplifier employing digital technique. [Citation Graph (, )][DBLP ] Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing. [Citation Graph (, )][DBLP ] Mixed-domain system representation using Volterra series. [Citation Graph (, )][DBLP ] A new orthogonal online digital calibration for time-interleaved analog-to-digital converters. [Citation Graph (, )][DBLP ] A Dual-Vt low leakage SRAM array robust to process variations. [Citation Graph (, )][DBLP ] A portless SRAM Cell using stunted wordline drivers. [Citation Graph (, )][DBLP ] Presetting pulse-based flip-flop. [Citation Graph (, )][DBLP ] High speed digital CMOS divide-by-N fequency divider. [Citation Graph (, )][DBLP ] A design methodology for logic paths tolerant to local intra-die variations. [Citation Graph (, )][DBLP ] An experimental study on multi-island structures for single-electron tunneling based threshold logic. [Citation Graph (, )][DBLP ] Limits to a correct operation in RTD-based ternary inverters. [Citation Graph (, )][DBLP ] An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. [Citation Graph (, )][DBLP ] Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. [Citation Graph (, )][DBLP ] Microstrip stepped impedance lowpass filters based on the maxwell-wagner polarization mechanism. [Citation Graph (, )][DBLP ] Early detection of all-zero block in H.264 with new rate-quantization models. [Citation Graph (, )][DBLP ] A fast adaptive quantization matrix selection method in H.264/AVC. [Citation Graph (, )][DBLP ] A model parameter and MAD prediction scheme for h.264 macroblock layer rate control. [Citation Graph (, )][DBLP ] Avoiding unnecessary frame memory access and multi-frame motion estimation computation in H.264/AVC. [Citation Graph (, )][DBLP ] Complexity and memory efficient GOP structures supporting VCR functionalities in H.264/AVC. [Citation Graph (, )][DBLP ] Does the brain really outperform Rent's rule? [Citation Graph (, )][DBLP ] LVDS interface for AER links with burst mode operation capability. [Citation Graph (, )][DBLP ] A serial communication infrastructure for multi-chip address event systems. [Citation Graph (, )][DBLP ] Fully digital AER convolution chip for vision processing. [Citation Graph (, )][DBLP ] A CMOS high IIP2 mixer for multi-standard receivers. [Citation Graph (, )][DBLP ] An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder. [Citation Graph (, )][DBLP ] 3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique. [Citation Graph (, )][DBLP ] An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. [Citation Graph (, )][DBLP ] A UWB CMOS 0.13µm low-noise amplifier with dual loop negative feedback. [Citation Graph (, )][DBLP ] Switching activity estimation for shift-and-add based constant multipliers. [Citation Graph (, )][DBLP ] High-speed modular multiplication design for public-key cryptosystems. [Citation Graph (, )][DBLP ] Performance analysis of flagged prefix adders with logical effort. [Citation Graph (, )][DBLP ] A novel decimal-to-decimal logarithmic converter. [Citation Graph (, )][DBLP ] Low-power logarithmic number system addition/subtraction and their impact on digital filters. [Citation Graph (, )][DBLP ] Selective enhancement of space-time broadband spiral-waves using 2D IIR digital filters. [Citation Graph (, )][DBLP ] Efficient design of delta operator based 2-D IIR filters using symmetrical decomposition. [Citation Graph (, )][DBLP ] Video coding with pixel-aligned directional adaptive interpolation filters. [Citation Graph (, )][DBLP ] Image deringing using quadtree based block-shift filtering. [Citation Graph (, )][DBLP ] Statistical detector for wavelet-based image watermarking using modified GH PDF. [Citation Graph (, )][DBLP ] Parameter variation analysis for voltage controlled oscillators in phase-locked loops. [Citation Graph (, )][DBLP ] Oscillation-based DFT for second-order OTA-C filters. [Citation Graph (, )][DBLP ] Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm. [Citation Graph (, )][DBLP ] Design methodology for CMOS distributed amplifiers. [Citation Graph (, )][DBLP ] A methodology for efficient design of analog circuits using an automated simulation based synthesis tool. [Citation Graph (, )][DBLP ] Low-power traceback MAP decoding for double-binary convolutional turbo decoder. [Citation Graph (, )][DBLP ] Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling. [Citation Graph (, )][DBLP ] Analog decoding of trellis coded modulation for multi-level flash memories. [Citation Graph (, )][DBLP ] Current-mode memory cell with power down phase for discrete time analog iterative decoders. [Citation Graph (, )][DBLP ] Multi-mode message passing switch networks applied for QC-LDPC decoder. [Citation Graph (, )][DBLP ] Synchronization of first-order time-delay systems generating n-scroll chaotic attractors. [Citation Graph (, )][DBLP ] An efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps. [Citation Graph (, )][DBLP ] Rigorous study of short periodic orbits for the Lorenz system. [Citation Graph (, )][DBLP ] Multi-wing butterfly attractors from the modified Lorenz systems. [Citation Graph (, )][DBLP ] Formulation and analysis of high-dimensional chaotic maps. [Citation Graph (, )][DBLP ] Advanced IC technology - opportunities and challenges. [Citation Graph (, )][DBLP ] Interconnect design and limitations in nanoscale technologies. [Citation Graph (, )][DBLP ] Electrical modeling and characterization of 3-D vias. [Citation Graph (, )][DBLP ] Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. [Citation Graph (, )][DBLP ] Performance analysis of optimized carbon nanotube interconnect. [Citation Graph (, )][DBLP ] ROM based logic (RBL) design: High-performance and low-power adders. [Citation Graph (, )][DBLP ] Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. [Citation Graph (, )][DBLP ] A low-voltage latch-adder based tree multiplier. [Citation Graph (, )][DBLP ] Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2^{m} ). [Citation Graph (, )][DBLP ] Data reuse analysis of local stereo matching. [Citation Graph (, )][DBLP ] Semi-implicit integration method for the time-domain simulation of thermal responses. [Citation Graph (, )][DBLP ] 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. [Citation Graph (, )][DBLP ] Design of self-powered wireless system-on-a-chip sensor nodes for hostile environments. [Citation Graph (, )][DBLP ] Device degradation and resilient computing. [Citation Graph (, )][DBLP ] Adaptive error control for reliable systems-on-chip. [Citation Graph (, )][DBLP ] Hardware-oriented image inpainting for perceptual I-frame error concealment. [Citation Graph (, )][DBLP ] Realizing high throughput transforms of H.264/AVC. [Citation Graph (, )][DBLP ] VLSI friendly computation reduction scheme in H.264/AVC motion estimation. [Citation Graph (, )][DBLP ] A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. [Citation Graph (, )][DBLP ] A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis. [Citation Graph (, )][DBLP ] A digital circuit design of hyperbolic tangent sigmoid function for neural networks. [Citation Graph (, )][DBLP ] Analog VLSI implementation of support vector machine learning and classification. [Citation Graph (, )][DBLP ] SOM with False-Neighbor degree and its behaviors. [Citation Graph (, )][DBLP ] Reservoir optimization in recurrent neural networks using kronecker kernels. [Citation Graph (, )][DBLP ] A neurofuzzy selfmade network with output dependable on a single parameter. [Citation Graph (, )][DBLP ] Foundational-circuit-based spice simulation. [Citation Graph (, )][DBLP ] Synthesis of RF CMOS Low Noise Amplifiers. [Citation Graph (, )][DBLP ] Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach. [Citation Graph (, )][DBLP ] Analytical modeling of common-gate low noise amplifiers. [Citation Graph (, )][DBLP ] Analog design retargeting by design knowledge reuse and circuit synthesis. [Citation Graph (, )][DBLP ] 1-V continuously tunable CMOS bulk-driven transconductor for Gm-C filters. [Citation Graph (, )][DBLP ] A CMOS 750MHz fifth-order continuous-time linear phase lowpass filter with gain boost. [Citation Graph (, )][DBLP ] An inverse filter realisation of a single scale Inverse continuous wavelet transform. [Citation Graph (, )][DBLP ] A floating-gate transistor based continuous-time analog adaptive filter. [Citation Graph (, )][DBLP ] A CMOS linear tunable transconductor for continuous-time tunable Gm-C filters. [Citation Graph (, )][DBLP ] An IIP2 calibration technique for CMOS multi-standard mixers. [Citation Graph (, )][DBLP ] Multi-band combined LNA and mixer. [Citation Graph (, )][DBLP ] A reconfigurable A/D converter for 4G wireless systems. [Citation Graph (, )][DBLP ] AMBA AHB bus potocol checker with efficient debugging mechanism. [Citation Graph (, )][DBLP ] A low complexity complex QR factorization design for signal detection in MIMO OFDM systems. [Citation Graph (, )][DBLP ] A novel approach for K-best MIMO detection and its VLSI implementation. [Citation Graph (, )][DBLP ] Scalable VLSI architecture for K-best lattice decoders. [Citation Graph (, )][DBLP ] FPGA implementation of a factorization processor for soft-decision reed-solomon decoding. [Citation Graph (, )][DBLP ] Analysis of CORDIC-based triangularization for MIMO MMSE filtering. [Citation Graph (, )][DBLP ] Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. [Citation Graph (, )][DBLP ] Optimal frame synchronization for DVB-S2. [Citation Graph (, )][DBLP ] A high-speed four-parallel radix-2^{4} FFT/IFFT processor for UWB applications. [Citation Graph (, )][DBLP ] A low-power V-band CMOS low-noise amplifier using current-sharing technique. [Citation Graph (, )][DBLP ] Bandwidth extension for ultra-wideband CMOS low-noise amplifiers. [Citation Graph (, )][DBLP ] A single-chip UMTS receiver with integrated digital frontend in 0.13 µm CMOS. [Citation Graph (, )][DBLP ] A low-power RF front-end for 2.5 GHz receivers. [Citation Graph (, )][DBLP ] A 24GHz low-power CMOS receiver design. [Citation Graph (, )][DBLP ] Design of Class-E power VCO in 65nm CMOS technology: Application to RF transmitter architecture. [Citation Graph (, )][DBLP ] A 6-11GHz multi-phase VCO design with active inductors. [Citation Graph (, )][DBLP ] A quadrature oscillator using simplified phase and amplitude calibration. [Citation Graph (, )][DBLP ] A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications. [Citation Graph (, )][DBLP ] A low-phase-noise LC QVCO with bottom-series coupling and capacitor tapping. [Citation Graph (, )][DBLP ] "Time borrowing" technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer. [Citation Graph (, )][DBLP ] Protocol-level performance analysis for anti-collision protocols in RFID systems. [Citation Graph (, )][DBLP ] Two bit-level pipelined viterbi decoder for high-performance UWB applications. [Citation Graph (, )][DBLP ] A novel digitally controlled low noise ring oscillator. [Citation Graph (, )][DBLP ] A new packet detection algorithm for IEEE 802.15.4a DBO-CSS in AWGN channel. [Citation Graph (, )][DBLP ] Video decoder embedded with temporal LMMSE denoising filter. [Citation Graph (, )][DBLP ] Image sensor with focal plane polarization sensitivity. [Citation Graph (, )][DBLP ] Self-timed vertacolor dichromatic vision sensor for low power pattern detection. [Citation Graph (, )][DBLP ] Steering with an aVLSI motion detection chip. [Citation Graph (, )][DBLP ] A micro-power asynchronous contrast-based vision sensor wakes-up on motion. [Citation Graph (, )][DBLP ] AER-based robotic closed-loop control system. [Citation Graph (, )][DBLP ] Configuring silicon neural networks using genetic algorithms. [Citation Graph (, )][DBLP ] A bio-inspired closed-loop insulin delivery based on the silicon pancreatic beta-cell. [Citation Graph (, )][DBLP ] Image convolution using a probabilistic mapper on USB-AER board. [Citation Graph (, )][DBLP ] Real time signal reconstruction from spikes on a digital signal processor. [Citation Graph (, )][DBLP ] A 1.2mW CMOS temporal-difference image sensor for sensor networks. [Citation Graph (, )][DBLP ] A novel refractometer architecture. [Citation Graph (, )][DBLP ] High throughput quantification system for egg populations in caenorhabditis elegans. [Citation Graph (, )][DBLP ] Neuromorphic implementation of active gaze and vergence control. [Citation Graph (, )][DBLP ] A handheld fluorometer for measuring cellular metabolism. [Citation Graph (, )][DBLP ] High-speed adaptive RF phased array. [Citation Graph (, )][DBLP ] Distraction-related EEG dynamics in virtual reality driving simulation. [Citation Graph (, )][DBLP ] Finite element modeling of tissue for optimal ultrasonic transducer array design. [Citation Graph (, )][DBLP ] Calibration and characterization of self-powered floating-gate sensor arrays for long-term fatigue monitoring. [Citation Graph (, )][DBLP ] A Low noise CMOS image sensor with an emission filter for fluorescence applications. [Citation Graph (, )][DBLP ] Low-power differential photoplethysmographic pulse transit time detector for ambulatory cardiovascular monitoring. [Citation Graph (, )][DBLP ] System for thermal measurement of pulse-transit-time. [Citation Graph (, )][DBLP ] Application of implantable wireless biomicrosystem for monitoring electrode-nerve impedance of animal after sciatic nerve injury. [Citation Graph (, )][DBLP ] Analogue/digital interface and communications aspects in a multi-channel ENG recording asic. [Citation Graph (, )][DBLP ] Design of second order digital differentiator using Richardson extrapolation and fractional delay. [Citation Graph (, )][DBLP ] Gramian-preserving frequency transformation for linear discrete-time systems using normalized lattice structure. [Citation Graph (, )][DBLP ] Robust analytical design of equiripple comb FIR filters. [Citation Graph (, )][DBLP ] IIR digital filter design via orthogonal projection of singular perturbational model reduction. [Citation Graph (, )][DBLP ] Adaptive channel equalization: A simplified approach using the quantized-LMF algorithm. [Citation Graph (, )][DBLP ] Special Fault Tolerant properties of FFT-based transform domain Adaptive Filters. [Citation Graph (, )][DBLP ] A new structure for sound reproduction system. [Citation Graph (, )][DBLP ] Tracking analysis of an adaptive IIR notch filter using gradient-based algorithm. [Citation Graph (, )][DBLP ] High resolution 2-D DOA estimation using second-order partial-differential of MUSIC spectrum. [Citation Graph (, )][DBLP ] Design of fractional delay FIR filter using discrete Fourier transform interpolation method. [Citation Graph (, )][DBLP ] Discrete fractional Fourier transform based on the eigenvectors of Grünbaum tridiagonal matrix. [Citation Graph (, )][DBLP ] Novel DCT-based real-valued discrete Gabor transform. [Citation Graph (, )][DBLP ] Fast operators for arbitrary warping maps. [Citation Graph (, )][DBLP ] Kalman filter for robust noise suppression in white and colored noises. [Citation Graph (, )][DBLP ] A novel algorithm for mobile station location estimation with none line of sight error using robust least M-estimation. [Citation Graph (, )][DBLP ] Model order selection for estimation of Common Acoustical Poles. [Citation Graph (, )][DBLP ] A novel technique for the design and DCGA optimization of bilinear-LDI lattice-based digital IF filters. [Citation Graph (, )][DBLP ] Compass tilt compensation algorithm using CORDIC. [Citation Graph (, )][DBLP ] CHStone: A benchmark program suite for practical C-based high-level synthesis. [Citation Graph (, )][DBLP ] Variability-aware design of subthreshold devices. [Citation Graph (, )][DBLP ] Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. [Citation Graph (, )][DBLP ] Thermal aware clock synthesis considering stochastic variation and correlations. [Citation Graph (, )][DBLP ] Sigma delta ADC with a dynamic reference for accurate temperature and voltage sensing. [Citation Graph (, )][DBLP ] Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer. [Citation Graph (, )][DBLP ] Multi-loop efficient sturdy MASH delta-sigma modulators. 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