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Conferences in DBLP

IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2008 (conf/iscas/2008)

  1. Enhancing industry participation in ISCAS and Circuits and Systems Society. [Citation Graph (, )][DBLP]

  2. Design of an ultra-low power SA-ADC with medium/high resolution and speed. [Citation Graph (, )][DBLP]

  3. A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. [Citation Graph (, )][DBLP]

  4. A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration. [Citation Graph (, )][DBLP]

  5. A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS. [Citation Graph (, )][DBLP]

  6. General analysis on the impact of phase-skew in time-interleaved ADCs. [Citation Graph (, )][DBLP]

  7. A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. [Citation Graph (, )][DBLP]

  8. HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV. [Citation Graph (, )][DBLP]

  9. Frame-parallel design strategy for high definition B-frame H.264/AVC encoder. [Citation Graph (, )][DBLP]

  10. Prediction-based real-time CABAC decoder for high definition H.264/AVC. [Citation Graph (, )][DBLP]

  11. A HW CABAC encoder with efficient context access scheme for H.264/AVC. [Citation Graph (, )][DBLP]

  12. New narrowband active noise control systems with significantly less computational requirements. [Citation Graph (, )][DBLP]

  13. Minimum redundancy MIMO radars. [Citation Graph (, )][DBLP]

  14. Sliding window online Kernel-based classification by projection mappings. [Citation Graph (, )][DBLP]

  15. Semi-blind data-selective algorithms for channel equalization. [Citation Graph (, )][DBLP]

  16. Fixed-point analysis of adaptive filters based on the EDS algorithm. [Citation Graph (, )][DBLP]

  17. BW extension in shunt feedback transimpedance amplifiers using negative miller capacitance. [Citation Graph (, )][DBLP]

  18. Tunable transimpedance amplifiers with constant bandwidth for optical communications. [Citation Graph (, )][DBLP]

  19. A simple class-AB transconductor in CMOS. [Citation Graph (, )][DBLP]

  20. A -72 dB @ 2 MHz IM3 CMOS tunable pseudo-differential transconductor. [Citation Graph (, )][DBLP]

  21. Bulk-driven gain-enhanced fully-differential amplifier for VT + 2Vdsat operation. [Citation Graph (, )][DBLP]

  22. Coefficient decimation approach for realizing reconfigurable finite impulse response filters. [Citation Graph (, )][DBLP]

  23. A reconfigurable multi-stage frequency response masking filter bank architecture for software defined radio receivers. [Citation Graph (, )][DBLP]

  24. Concept for an adaptive digital front-end for multi-mode wireless receivers. [Citation Graph (, )][DBLP]

  25. Filter bank based frequency-domain equalizers with diversity combining. [Citation Graph (, )][DBLP]

  26. Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. [Citation Graph (, )][DBLP]

  27. Network topology estimation through synchronization: A case study on quantum dot CNN. [Citation Graph (, )][DBLP]

  28. Solving ability of Hopfield Neural Network with scale-rule noise for QAP. [Citation Graph (, )][DBLP]

  29. Topology identification of an uncertain general complex dynamical network. [Citation Graph (, )][DBLP]

  30. Wave propagation in oscillators coupled by time-varying resistor with timing mismatch. [Citation Graph (, )][DBLP]

  31. Constraint modules: An introduction. [Citation Graph (, )][DBLP]

  32. Recently developed approaches for solving blind deconvolution of MIMO-IIR Systems: Super-exponential and eigenvector methods. [Citation Graph (, )][DBLP]

  33. Semi-blind channel estimation of MIMO-OFDM systems with pulse shaping. [Citation Graph (, )][DBLP]

  34. Perturbation analysis of subspace-based semi-blind MIMO channel estimation approaches. [Citation Graph (, )][DBLP]

  35. Blind identification of MIMO channels with periodic precoders. [Citation Graph (, )][DBLP]

  36. Blind block synchronization algorithms in cyclic prefix systems. [Citation Graph (, )][DBLP]

  37. Power-delay optimization in MCML tapered buffers. [Citation Graph (, )][DBLP]

  38. Improving the power-delay product in SCL circuits using source follower output stage. [Citation Graph (, )][DBLP]

  39. An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. [Citation Graph (, )][DBLP]

  40. Transistor-level programmable MOS analog IC with body biasing. [Citation Graph (, )][DBLP]

  41. High speed serial interface for mobile LCD driver IC. [Citation Graph (, )][DBLP]

  42. A two-stator MEMS power generator for cardiac pacemakers. [Citation Graph (, )][DBLP]

  43. A fully differential CMOS capacitance sensor design, testing and array architecture. [Citation Graph (, )][DBLP]

  44. Graphene nanoribbon field-effect transistors. [Citation Graph (, )][DBLP]

  45. Analyzing mixed carbon nanotube bundles: A current density study. [Citation Graph (, )][DBLP]

  46. Carbon nanotube circuit design choices in the presence of metallic tubes. [Citation Graph (, )][DBLP]

  47. Bilateral design of mm-wave LNA and receiver front-end in 90nm CMOS. [Citation Graph (, )][DBLP]

  48. A 700Mbit/s CMOS capacitive feedback front-end amplifier with automatic gain control for broadband optical wireless links. [Citation Graph (, )][DBLP]

  49. 124dB.Hz2/3 Dynamic range transimpedance amplifier for electronic-photonic channelizer. [Citation Graph (, )][DBLP]

  50. A 10 Gb/s optical receiver in 0.25 µm silicon-on-sapphire CMOS. [Citation Graph (, )][DBLP]

  51. An optically powered, free space optical communications receiver. [Citation Graph (, )][DBLP]

  52. Minimum energy broadcasting in wireless networks (extended abstract). [Citation Graph (, )][DBLP]

  53. Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs. [Citation Graph (, )][DBLP]

  54. A method for verifying deadlock freedom and liveness of petri nets. [Citation Graph (, )][DBLP]

  55. On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract). [Citation Graph (, )][DBLP]

  56. Versatile graphs for tail-biting convolutional codes. [Citation Graph (, )][DBLP]

  57. Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC. [Citation Graph (, )][DBLP]

  58. A 10-bit 8.3MS/s switched-current successive approximation ADC for column-parallel imagers. [Citation Graph (, )][DBLP]

  59. Predictive timing error calibration technique for RF current-steering DACs. [Citation Graph (, )][DBLP]

  60. New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise. [Citation Graph (, )][DBLP]

  61. Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. [Citation Graph (, )][DBLP]

  62. Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. [Citation Graph (, )][DBLP]

  63. A fault-tolerant, DFA-resistant AES core. [Citation Graph (, )][DBLP]

  64. Modeling and exploration of a reconfigurable architecture for digital holographic imaging. [Citation Graph (, )][DBLP]

  65. Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems. [Citation Graph (, )][DBLP]

  66. A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. [Citation Graph (, )][DBLP]

  67. Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression. [Citation Graph (, )][DBLP]

  68. Multiframe image super-resolution using quasi-newton algorithms. [Citation Graph (, )][DBLP]

  69. Application of scalable visual sensitivity profile in image and video coding. [Citation Graph (, )][DBLP]

  70. Modeling of the DCT coefficients of images. [Citation Graph (, )][DBLP]

  71. Target region-aware tone reproduction. [Citation Graph (, )][DBLP]

  72. A 1.5 bit 5th order CT/DT delta sigma class D amplifier with power efficiency improvement. [Citation Graph (, )][DBLP]

  73. PSRR of bridge-tied load PWM Class D Amps. [Citation Graph (, )][DBLP]

  74. High slew rate two stage A/AB and AB/AB op-amps with phase lead compensation at output node and local common mode feedback. [Citation Graph (, )][DBLP]

  75. A simple approach for the implementation of CMOS amplifiers with constant bandwidth independent of gain. [Citation Graph (, )][DBLP]

  76. A novel topology in RNMC amplifiers with single miller compensation capacitor. [Citation Graph (, )][DBLP]

  77. VLSI architecture for data-reduced steering matrix feedback in MIMO systems. [Citation Graph (, )][DBLP]

  78. Hardware-efficient steering matrix computation architecture for MIMO communication systems. [Citation Graph (, )][DBLP]

  79. A single-FPGA multipath MIMO fading channel simulator. [Citation Graph (, )][DBLP]

  80. A modified MMSE-SD soft detector for coded MIMO-OFDM systems. [Citation Graph (, )][DBLP]

  81. The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection. [Citation Graph (, )][DBLP]

  82. Introducing Complex Oscillation Based Test: an application example targeting Analog to Digital Converters. [Citation Graph (, )][DBLP]

  83. Stability study of the TCP-RED system using detrended fluctuation analysis. [Citation Graph (, )][DBLP]

  84. Rotation map with a controlling segment and its application to A/D converters. [Citation Graph (, )][DBLP]

  85. A quantum-dot light-harvesting architecture using deterministic phase control. [Citation Graph (, )][DBLP]

  86. A method based on a genetic algorithm to find PWL approximations of multivariate nonlinear functions. [Citation Graph (, )][DBLP]

  87. General-pupose technology for a general-purpose nervous system. [Citation Graph (, )][DBLP]

  88. Pulse-based signal compression for implanted neural recording systems. [Citation Graph (, )][DBLP]

  89. Radios for the brain? a practical micropower sensing and algorithm architecture for neurostimulators. [Citation Graph (, )][DBLP]

  90. Implant electronics for intraocular epiretinal neuro-stimulators. [Citation Graph (, )][DBLP]

  91. Stimulation and recording of neural tissue, closing the loop on the artifact. [Citation Graph (, )][DBLP]

  92. Power-aware topology optimization for networks-on-chips. [Citation Graph (, )][DBLP]

  93. Design target exploration for meeting time-to-market using pareto analysis. [Citation Graph (, )][DBLP]

  94. A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design. [Citation Graph (, )][DBLP]

  95. A robust alternate repeater technique for high performance busses in the multi-core era. [Citation Graph (, )][DBLP]

  96. Input port reduction for efficient substrate extraction in large scale IC's. [Citation Graph (, )][DBLP]

  97. Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. [Citation Graph (, )][DBLP]

  98. Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. [Citation Graph (, )][DBLP]

  99. Low variation current source for 90nm CMOS. [Citation Graph (, )][DBLP]

  100. Design of process variation tolerant radio frequency low noise amplifier. [Citation Graph (, )][DBLP]

  101. Binary translation process to optimize nanowire arrays usage. [Citation Graph (, )][DBLP]

  102. Cross-dimensional quality assessment for low bitrate video. [Citation Graph (, )][DBLP]

  103. Backward-forward distortion minimization for binary images data hiding. [Citation Graph (, )][DBLP]

  104. Peceptual distortion metric based on wavelet frequency sensitivity and multiple visual fixations. [Citation Graph (, )][DBLP]

  105. Adaptive feature selection for digital camera source identification. [Citation Graph (, )][DBLP]

  106. On the quality assessment of sound signals. [Citation Graph (, )][DBLP]

  107. A two-neuron cross-correlation circuit with a wide and continuous range of time delay. [Citation Graph (, )][DBLP]

  108. Fall detection using an address-event temporal contrast vision sensor. [Citation Graph (, )][DBLP]

  109. Bifurcations in a silicon neuron. [Citation Graph (, )][DBLP]

  110. A biophysically based dendrite model using programmable floating-gate devices. [Citation Graph (, )][DBLP]

  111. The time derivative neuron. [Citation Graph (, )][DBLP]

  112. Quadrature generation techniques for frequency multiplication based oscillators. [Citation Graph (, )][DBLP]

  113. Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range. [Citation Graph (, )][DBLP]

  114. A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit. [Citation Graph (, )][DBLP]

  115. A charge-pump based 0.35µm CMOS RF switch driver for multi-standard operations. [Citation Graph (, )][DBLP]

  116. Low-voltage bulk-driven mixer with on-chip balun. [Citation Graph (, )][DBLP]

  117. A 65nm 10GHz pipelined MAC structure. [Citation Graph (, )][DBLP]

  118. A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). [Citation Graph (, )][DBLP]

  119. An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. [Citation Graph (, )][DBLP]

  120. A high performance floating-point special function unit using constrained piecewise quadratic approximation. [Citation Graph (, )][DBLP]

  121. Novel VLSI implementation of Peano-Hilbert curve address generator. [Citation Graph (, )][DBLP]

  122. The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. [Citation Graph (, )][DBLP]

  123. A novel CAVLC architecture for H.264 Video encoding at high bit-rate. [Citation Graph (, )][DBLP]

  124. Analysis of video filtering on the cell processor. [Citation Graph (, )][DBLP]

  125. Efficient intra-4×4 mode decision based on bit-rate estimation in H.264/AVC. [Citation Graph (, )][DBLP]

  126. Bit-depth expansion by adaptive filter. [Citation Graph (, )][DBLP]

  127. Automated conversion of Simulink designs to analog hardware on an FPAA. [Citation Graph (, )][DBLP]

  128. A novel approach for automated model generation. [Citation Graph (, )][DBLP]

  129. Accurate and reusable macromodeling technique using a fuzzy-logic approach. [Citation Graph (, )][DBLP]

  130. Reducing the effects of component mismatch by using relative size information. [Citation Graph (, )][DBLP]

  131. Capacitance ratio approximation in SC filters via genetic algorithm. [Citation Graph (, )][DBLP]

  132. VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. [Citation Graph (, )][DBLP]

  133. Enhanced delta-based layered decoding of WiMAX QC-LDPC codes. [Citation Graph (, )][DBLP]

  134. Switching activity reducing layered decoding algorithm for LDPC codes. [Citation Graph (, )][DBLP]

  135. A dual-core programmable decoder for LDPC convolutional codes. [Citation Graph (, )][DBLP]

  136. Adaptive quantization in min-sum based irregular LDPC decoder. [Citation Graph (, )][DBLP]

  137. State discontinuity analysis of linear switched systems via energy function optimization. [Citation Graph (, )][DBLP]

  138. Injection locking conditions under small periodic excitations. [Citation Graph (, )][DBLP]

  139. Linear probability feedback processes. [Citation Graph (, )][DBLP]

  140. A comparative study of the new LQ-MCS control on an automotive electro-mechanical system. [Citation Graph (, )][DBLP]

  141. Stability analysis and control of bifurcations of parallel connected DC/DC converters using the monodromy matrix. [Citation Graph (, )][DBLP]

  142. Digitally enhanced analog circuits: System aspects. [Citation Graph (, )][DBLP]

  143. Performance enhancement of linear power amplifier employing digital technique. [Citation Graph (, )][DBLP]

  144. Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing. [Citation Graph (, )][DBLP]

  145. Mixed-domain system representation using Volterra series. [Citation Graph (, )][DBLP]

  146. A new orthogonal online digital calibration for time-interleaved analog-to-digital converters. [Citation Graph (, )][DBLP]

  147. A Dual-Vt low leakage SRAM array robust to process variations. [Citation Graph (, )][DBLP]

  148. A portless SRAM Cell using stunted wordline drivers. [Citation Graph (, )][DBLP]

  149. Presetting pulse-based flip-flop. [Citation Graph (, )][DBLP]

  150. High speed digital CMOS divide-by-N fequency divider. [Citation Graph (, )][DBLP]

  151. A design methodology for logic paths tolerant to local intra-die variations. [Citation Graph (, )][DBLP]

  152. An experimental study on multi-island structures for single-electron tunneling based threshold logic. [Citation Graph (, )][DBLP]

  153. Limits to a correct operation in RTD-based ternary inverters. [Citation Graph (, )][DBLP]

  154. An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. [Citation Graph (, )][DBLP]

  155. Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. [Citation Graph (, )][DBLP]

  156. Microstrip stepped impedance lowpass filters based on the maxwell-wagner polarization mechanism. [Citation Graph (, )][DBLP]

  157. Early detection of all-zero block in H.264 with new rate-quantization models. [Citation Graph (, )][DBLP]

  158. A fast adaptive quantization matrix selection method in H.264/AVC. [Citation Graph (, )][DBLP]

  159. A model parameter and MAD prediction scheme for h.264 macroblock layer rate control. [Citation Graph (, )][DBLP]

  160. Avoiding unnecessary frame memory access and multi-frame motion estimation computation in H.264/AVC. [Citation Graph (, )][DBLP]

  161. Complexity and memory efficient GOP structures supporting VCR functionalities in H.264/AVC. [Citation Graph (, )][DBLP]

  162. Does the brain really outperform Rent's rule? [Citation Graph (, )][DBLP]

  163. LVDS interface for AER links with burst mode operation capability. [Citation Graph (, )][DBLP]

  164. A serial communication infrastructure for multi-chip address event systems. [Citation Graph (, )][DBLP]

  165. Fully digital AER convolution chip for vision processing. [Citation Graph (, )][DBLP]

  166. A CMOS high IIP2 mixer for multi-standard receivers. [Citation Graph (, )][DBLP]

  167. An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder. [Citation Graph (, )][DBLP]

  168. 3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique. [Citation Graph (, )][DBLP]

  169. An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. [Citation Graph (, )][DBLP]

  170. A UWB CMOS 0.13µm low-noise amplifier with dual loop negative feedback. [Citation Graph (, )][DBLP]

  171. Switching activity estimation for shift-and-add based constant multipliers. [Citation Graph (, )][DBLP]

  172. High-speed modular multiplication design for public-key cryptosystems. [Citation Graph (, )][DBLP]

  173. Performance analysis of flagged prefix adders with logical effort. [Citation Graph (, )][DBLP]

  174. A novel decimal-to-decimal logarithmic converter. [Citation Graph (, )][DBLP]

  175. Low-power logarithmic number system addition/subtraction and their impact on digital filters. [Citation Graph (, )][DBLP]

  176. Selective enhancement of space-time broadband spiral-waves using 2D IIR digital filters. [Citation Graph (, )][DBLP]

  177. Efficient design of delta operator based 2-D IIR filters using symmetrical decomposition. [Citation Graph (, )][DBLP]

  178. Video coding with pixel-aligned directional adaptive interpolation filters. [Citation Graph (, )][DBLP]

  179. Image deringing using quadtree based block-shift filtering. [Citation Graph (, )][DBLP]

  180. Statistical detector for wavelet-based image watermarking using modified GH PDF. [Citation Graph (, )][DBLP]

  181. Parameter variation analysis for voltage controlled oscillators in phase-locked loops. [Citation Graph (, )][DBLP]

  182. Oscillation-based DFT for second-order OTA-C filters. [Citation Graph (, )][DBLP]

  183. Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm. [Citation Graph (, )][DBLP]

  184. Design methodology for CMOS distributed amplifiers. [Citation Graph (, )][DBLP]

  185. A methodology for efficient design of analog circuits using an automated simulation based synthesis tool. [Citation Graph (, )][DBLP]

  186. Low-power traceback MAP decoding for double-binary convolutional turbo decoder. [Citation Graph (, )][DBLP]

  187. Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling. [Citation Graph (, )][DBLP]

  188. Analog decoding of trellis coded modulation for multi-level flash memories. [Citation Graph (, )][DBLP]

  189. Current-mode memory cell with power down phase for discrete time analog iterative decoders. [Citation Graph (, )][DBLP]

  190. Multi-mode message passing switch networks applied for QC-LDPC decoder. [Citation Graph (, )][DBLP]

  191. Synchronization of first-order time-delay systems generating n-scroll chaotic attractors. [Citation Graph (, )][DBLP]

  192. An efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps. [Citation Graph (, )][DBLP]

  193. Rigorous study of short periodic orbits for the Lorenz system. [Citation Graph (, )][DBLP]

  194. Multi-wing butterfly attractors from the modified Lorenz systems. [Citation Graph (, )][DBLP]

  195. Formulation and analysis of high-dimensional chaotic maps. [Citation Graph (, )][DBLP]

  196. Advanced IC technology - opportunities and challenges. [Citation Graph (, )][DBLP]

  197. Interconnect design and limitations in nanoscale technologies. [Citation Graph (, )][DBLP]

  198. Electrical modeling and characterization of 3-D vias. [Citation Graph (, )][DBLP]

  199. Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. [Citation Graph (, )][DBLP]

  200. Performance analysis of optimized carbon nanotube interconnect. [Citation Graph (, )][DBLP]

  201. ROM based logic (RBL) design: High-performance and low-power adders. [Citation Graph (, )][DBLP]

  202. Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. [Citation Graph (, )][DBLP]

  203. A low-voltage latch-adder based tree multiplier. [Citation Graph (, )][DBLP]

  204. Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). [Citation Graph (, )][DBLP]

  205. Data reuse analysis of local stereo matching. [Citation Graph (, )][DBLP]

  206. Semi-implicit integration method for the time-domain simulation of thermal responses. [Citation Graph (, )][DBLP]

  207. 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. [Citation Graph (, )][DBLP]

  208. Design of self-powered wireless system-on-a-chip sensor nodes for hostile environments. [Citation Graph (, )][DBLP]

  209. Device degradation and resilient computing. [Citation Graph (, )][DBLP]

  210. Adaptive error control for reliable systems-on-chip. [Citation Graph (, )][DBLP]

  211. Hardware-oriented image inpainting for perceptual I-frame error concealment. [Citation Graph (, )][DBLP]

  212. Realizing high throughput transforms of H.264/AVC. [Citation Graph (, )][DBLP]

  213. VLSI friendly computation reduction scheme in H.264/AVC motion estimation. [Citation Graph (, )][DBLP]

  214. A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. [Citation Graph (, )][DBLP]

  215. A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis. [Citation Graph (, )][DBLP]

  216. A digital circuit design of hyperbolic tangent sigmoid function for neural networks. [Citation Graph (, )][DBLP]

  217. Analog VLSI implementation of support vector machine learning and classification. [Citation Graph (, )][DBLP]

  218. SOM with False-Neighbor degree and its behaviors. [Citation Graph (, )][DBLP]

  219. Reservoir optimization in recurrent neural networks using kronecker kernels. [Citation Graph (, )][DBLP]

  220. A neurofuzzy selfmade network with output dependable on a single parameter. [Citation Graph (, )][DBLP]

  221. Foundational-circuit-based spice simulation. [Citation Graph (, )][DBLP]

  222. Synthesis of RF CMOS Low Noise Amplifiers. [Citation Graph (, )][DBLP]

  223. Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach. [Citation Graph (, )][DBLP]

  224. Analytical modeling of common-gate low noise amplifiers. [Citation Graph (, )][DBLP]

  225. Analog design retargeting by design knowledge reuse and circuit synthesis. [Citation Graph (, )][DBLP]

  226. 1-V continuously tunable CMOS bulk-driven transconductor for Gm-C filters. [Citation Graph (, )][DBLP]

  227. A CMOS 750MHz fifth-order continuous-time linear phase lowpass filter with gain boost. [Citation Graph (, )][DBLP]

  228. An inverse filter realisation of a single scale Inverse continuous wavelet transform. [Citation Graph (, )][DBLP]

  229. A floating-gate transistor based continuous-time analog adaptive filter. [Citation Graph (, )][DBLP]

  230. A CMOS linear tunable transconductor for continuous-time tunable Gm-C filters. [Citation Graph (, )][DBLP]

  231. An IIP2 calibration technique for CMOS multi-standard mixers. [Citation Graph (, )][DBLP]

  232. Multi-band combined LNA and mixer. [Citation Graph (, )][DBLP]

  233. A reconfigurable A/D converter for 4G wireless systems. [Citation Graph (, )][DBLP]

  234. AMBA AHB bus potocol checker with efficient debugging mechanism. [Citation Graph (, )][DBLP]

  235. A low complexity complex QR factorization design for signal detection in MIMO OFDM systems. [Citation Graph (, )][DBLP]

  236. A novel approach for K-best MIMO detection and its VLSI implementation. [Citation Graph (, )][DBLP]

  237. Scalable VLSI architecture for K-best lattice decoders. [Citation Graph (, )][DBLP]

  238. FPGA implementation of a factorization processor for soft-decision reed-solomon decoding. [Citation Graph (, )][DBLP]

  239. Analysis of CORDIC-based triangularization for MIMO MMSE filtering. [Citation Graph (, )][DBLP]

  240. Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. [Citation Graph (, )][DBLP]

  241. Optimal frame synchronization for DVB-S2. [Citation Graph (, )][DBLP]

  242. A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. [Citation Graph (, )][DBLP]

  243. A low-power V-band CMOS low-noise amplifier using current-sharing technique. [Citation Graph (, )][DBLP]

  244. Bandwidth extension for ultra-wideband CMOS low-noise amplifiers. [Citation Graph (, )][DBLP]

  245. A single-chip UMTS receiver with integrated digital frontend in 0.13 µm CMOS. [Citation Graph (, )][DBLP]

  246. A low-power RF front-end for 2.5 GHz receivers. [Citation Graph (, )][DBLP]

  247. A 24GHz low-power CMOS receiver design. [Citation Graph (, )][DBLP]

  248. Design of Class-E power VCO in 65nm CMOS technology: Application to RF transmitter architecture. [Citation Graph (, )][DBLP]

  249. A 6-11GHz multi-phase VCO design with active inductors. [Citation Graph (, )][DBLP]

  250. A quadrature oscillator using simplified phase and amplitude calibration. [Citation Graph (, )][DBLP]

  251. A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications. [Citation Graph (, )][DBLP]

  252. A low-phase-noise LC QVCO with bottom-series coupling and capacitor tapping. [Citation Graph (, )][DBLP]

  253. "Time borrowing" technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer. [Citation Graph (, )][DBLP]

  254. Protocol-level performance analysis for anti-collision protocols in RFID systems. [Citation Graph (, )][DBLP]

  255. Two bit-level pipelined viterbi decoder for high-performance UWB applications. [Citation Graph (, )][DBLP]

  256. A novel digitally controlled low noise ring oscillator. [Citation Graph (, )][DBLP]

  257. A new packet detection algorithm for IEEE 802.15.4a DBO-CSS in AWGN channel. [Citation Graph (, )][DBLP]

  258. Video decoder embedded with temporal LMMSE denoising filter. [Citation Graph (, )][DBLP]

  259. Image sensor with focal plane polarization sensitivity. [Citation Graph (, )][DBLP]

  260. Self-timed vertacolor dichromatic vision sensor for low power pattern detection. [Citation Graph (, )][DBLP]

  261. Steering with an aVLSI motion detection chip. [Citation Graph (, )][DBLP]

  262. A micro-power asynchronous contrast-based vision sensor wakes-up on motion. [Citation Graph (, )][DBLP]

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  265. A bio-inspired closed-loop insulin delivery based on the silicon pancreatic beta-cell. [Citation Graph (, )][DBLP]

  266. Image convolution using a probabilistic mapper on USB-AER board. [Citation Graph (, )][DBLP]

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  272. A handheld fluorometer for measuring cellular metabolism. [Citation Graph (, )][DBLP]

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  274. Distraction-related EEG dynamics in virtual reality driving simulation. [Citation Graph (, )][DBLP]

  275. Finite element modeling of tissue for optimal ultrasonic transducer array design. [Citation Graph (, )][DBLP]

  276. Calibration and characterization of self-powered floating-gate sensor arrays for long-term fatigue monitoring. [Citation Graph (, )][DBLP]

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  280. Application of implantable wireless biomicrosystem for monitoring electrode-nerve impedance of animal after sciatic nerve injury. [Citation Graph (, )][DBLP]

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  284. Robust analytical design of equiripple comb FIR filters. [Citation Graph (, )][DBLP]

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  291. Design of fractional delay FIR filter using discrete Fourier transform interpolation method. [Citation Graph (, )][DBLP]

  292. Discrete fractional Fourier transform based on the eigenvectors of Grünbaum tridiagonal matrix. [Citation Graph (, )][DBLP]

  293. Novel DCT-based real-valued discrete Gabor transform. [Citation Graph (, )][DBLP]

  294. Fast operators for arbitrary warping maps. [Citation Graph (, )][DBLP]

  295. Kalman filter for robust noise suppression in white and colored noises. [Citation Graph (, )][DBLP]

  296. A novel algorithm for mobile station location estimation with none line of sight error using robust least M-estimation. [Citation Graph (, )][DBLP]

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  298. A novel technique for the design and DCGA optimization of bilinear-LDI lattice-based digital IF filters. [Citation Graph (, )][DBLP]

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  300. CHStone: A benchmark program suite for practical C-based high-level synthesis. [Citation Graph (, )][DBLP]

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  310. Robust wide range of supply-voltage operation using continuous adaptive size-ratio gates. [Citation Graph (, )][DBLP]

  311. Dynamic voltage and frequency scaling circuits with two supply voltages. [Citation Graph (, )][DBLP]

  312. Power optimization of weighted bit-product summation tree for elementary function generator. [Citation Graph (, )][DBLP]

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  314. Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. [Citation Graph (, )][DBLP]

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  317. Benefit of linearizing power amplifiers in multi-port amplifier subsystems. [Citation Graph (, )][DBLP]

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  319. Analytical solutions of the Class D inverter. [Citation Graph (, )][DBLP]

  320. Improved harmonic analysis of RC-active phase shift oscillators. [Citation Graph (, )][DBLP]

  321. A varactorless technique for tuning LC oscillators based on loop gain adjustment. [Citation Graph (, )][DBLP]

  322. Efficient model reduction of passive electrical networks with a large number of independent sources. [Citation Graph (, )][DBLP]

  323. Invariant sums of higher order sensitivities. [Citation Graph (, )][DBLP]

  324. Digital calibration of gain and linearity in a CMOS RF mixer. [Citation Graph (, )][DBLP]

  325. ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. [Citation Graph (, )][DBLP]

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  328. A new WiMAX sigma-delta modulator with constant-Q active inductors. [Citation Graph (, )][DBLP]

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  330. An efficient approach to model distortion in weakly nonlinear Gm - C filters. [Citation Graph (, )][DBLP]

  331. The effect of parameter mismatches in RF VCO. [Citation Graph (, )][DBLP]

  332. Study of zero-order holder discretization in single input sliding mode control systems. [Citation Graph (, )][DBLP]

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  335. Non-negative matrix factorization in bioinformatics: Towards understanding biological processes. [Citation Graph (, )][DBLP]

  336. Group learning using contrast NMF : Application to functional and structural MRI of schizophrenia. [Citation Graph (, )][DBLP]

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  339. HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture. [Citation Graph (, )][DBLP]

  340. Finding minimum interconnect sub-arrays in reconfigurable VLSI arrays. [Citation Graph (, )][DBLP]

  341. An efficient greedy approach to PLA folding. [Citation Graph (, )][DBLP]

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  343. An asynchronous spike event coding scheme for programmable analog arrays. [Citation Graph (, )][DBLP]

  344. A study on global robust stability of delayed full-range cellular neural networks. [Citation Graph (, )][DBLP]

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  347. Spiral waves in bio-inspired oscillatory media. [Citation Graph (, )][DBLP]

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  351. 3-D direction aligned wavelet transform for scalable video coding. [Citation Graph (, )][DBLP]

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  355. Low power image sensor with polymer polarization filters. [Citation Graph (, )][DBLP]

  356. Phototransistor image sensor in silicon on sapphire. [Citation Graph (, )][DBLP]

  357. A 256×256 separable transform CMOS imager. [Citation Graph (, )][DBLP]

  358. A Sub-µW fully programmable CMOS DPS for uncooled infrared fast imaging. [Citation Graph (, )][DBLP]

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  360. A new optimization approach for the automatic design of SigmaDelta-modulators. [Citation Graph (, )][DBLP]

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  362. Efficient fully-floating double-sampling integrator for DeltaSigma ADCs. [Citation Graph (, )][DBLP]

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  364. Active self supplied AC-DC converter for piezoelectric energy scavenging systems with supply independent bias. [Citation Graph (, )][DBLP]

  365. Low power and robust 7T dual-Vt SRAM circuit. [Citation Graph (, )][DBLP]

  366. 60µW SMR BAW oscillator designed in 65nm CMOS technology. [Citation Graph (, )][DBLP]

  367. A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers. [Citation Graph (, )][DBLP]

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  374. Delta discrete-time operator based realization procedure for low sensitivity sampled-data and digital ladder filters. [Citation Graph (, )][DBLP]

  375. Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor. [Citation Graph (, )][DBLP]

  376. On-chip RC measurement and calibration circuit using Wheatstone bridge. [Citation Graph (, )][DBLP]

  377. Direct-form SC filters with low frequency response sensitivity to the transfer function coefficients. [Citation Graph (, )][DBLP]

  378. A fast compact CMOS feedforward automatic gain control circuit. [Citation Graph (, )][DBLP]

  379. Impulse based scheme for crystal-less ULP radios. [Citation Graph (, )][DBLP]

  380. Efficient spacing scheme for a linearly interpolated lookup table predistorter. [Citation Graph (, )][DBLP]

  381. A tool for the fast distortion evaluation of non linear amplifiers in broadband transmission systems. [Citation Graph (, )][DBLP]

  382. Efficient coarse frequency synchronizer using serial correlator for DVB-S2. [Citation Graph (, )][DBLP]

  383. Design and implementation of a fully reconfigurable chipless RFID tag using Inkjet printing technology. [Citation Graph (, )][DBLP]

  384. Predictive control algorithm for phase-locked loops. [Citation Graph (, )][DBLP]

  385. A phase-frequency detector and a charge pump design for PLL applications. [Citation Graph (, )][DBLP]

  386. An alias-locked loop frequency synthesis architecture. [Citation Graph (, )][DBLP]

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  388. Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input. [Citation Graph (, )][DBLP]

  389. A CMOS image sensor with spiking pixels for retinal stimulation. [Citation Graph (, )][DBLP]

  390. A programmable ENG amplifier with passive EMG neutralization for FES applications. [Citation Graph (, )][DBLP]

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  395. Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. [Citation Graph (, )][DBLP]

  396. Utilizing synthesis to verify Boolean function models. [Citation Graph (, )][DBLP]

  397. Multi-clock pipeline structure for 802.11 a WLAN transceiver. [Citation Graph (, )][DBLP]

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  400. ASPA: Focal Plane digital processor array with asynchronous processing capabilities. [Citation Graph (, )][DBLP]

  401. Pixel parallel vessel tree extraction for a personal authentication system. [Citation Graph (, )][DBLP]

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  404. Super resolution of video using key frames. [Citation Graph (, )][DBLP]

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  418. Digitally-enhanced 2nd-order DeltaSigma modulator with unity-gain signal transfer function. [Citation Graph (, )][DBLP]

  419. A low power, process invariant keeper for high speed dynamic logic circuits. [Citation Graph (, )][DBLP]

  420. A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm. [Citation Graph (, )][DBLP]

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  422. Address compression for scalable load/store queue implementation. [Citation Graph (, )][DBLP]

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  424. Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. [Citation Graph (, )][DBLP]

  425. Pulse width and position modulation for fully digital audio amplifier. [Citation Graph (, )][DBLP]

  426. Direction of arrival estimation for speech sources using fourth order cross cumulants. [Citation Graph (, )][DBLP]

  427. Speech enhancement based on adaptive wavelet denoising on multitaper spectrum. [Citation Graph (, )][DBLP]

  428. A spectro-temporal algorithm for pitch frequency estimation from noisy observations. [Citation Graph (, )][DBLP]

  429. An adjustable CMOS floating resistor. [Citation Graph (, )][DBLP]

  430. Comparison of programmable linear resistors based on quasi-floating gate MOSFETs. [Citation Graph (, )][DBLP]

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  432. A simple modeling of the early voltage of MOSFETs in weak and moderate inversion. [Citation Graph (, )][DBLP]

  433. The low-power and low-area PWM by light intensity for photoflash in 0.35-µm CMOS. [Citation Graph (, )][DBLP]

  434. A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit. [Citation Graph (, )][DBLP]

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  436. A high-speed variable phase accumulator for an ADPLL architecture. [Citation Graph (, )][DBLP]

  437. Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling. [Citation Graph (, )][DBLP]

  438. The effect of noise propagation on phase noise in ring oscillators. [Citation Graph (, )][DBLP]

  439. Wireless neural signal acquisition with single low-power integrated circuit. [Citation Graph (, )][DBLP]

  440. HermesC: RF wireless low-power neural recording system for freely behaving primates. [Citation Graph (, )][DBLP]

  441. A clockless ultra low-noise low-power wireless implantable neural recording system. [Citation Graph (, )][DBLP]

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  443. Dual band LNA/mixer using conjugate matching for implantable biotelemetry. [Citation Graph (, )][DBLP]

  444. Self-tuned regenerative amplification and the hopf bifurcation. [Citation Graph (, )][DBLP]

  445. A 2-D silicon cochlea with an improved automatic quality factor control-loop. [Citation Graph (, )][DBLP]

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  447. Noise model, analysis and characterization of a differential active pixel sensor. [Citation Graph (, )][DBLP]

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  449. Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). [Citation Graph (, )][DBLP]

  450. Glitch-aware output switching activity from word-level statistics. [Citation Graph (, )][DBLP]

  451. Arithmetic module generator with algorithm optimization capability. [Citation Graph (, )][DBLP]

  452. ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. [Citation Graph (, )][DBLP]

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  454. An integrated patch-clamp amplifier for high-throughput planar patch-clamp systems. [Citation Graph (, )][DBLP]

  455. MEMS acoustic sensors for totally implantable hearing aid systems. [Citation Graph (, )][DBLP]

  456. System-on-chip ultrasonic transducer for dental tissue formation and stem cell growth and differentiation. [Citation Graph (, )][DBLP]

  457. Ultra-high ratio dilution microfluidic system for single strand DNA isolation. [Citation Graph (, )][DBLP]

  458. Computer aided simulation and verification of forward error-correcting biosensors. [Citation Graph (, )][DBLP]

  459. A multiple description image/video coding method by compressed sensing theory. [Citation Graph (, )][DBLP]

  460. Effective congestion and error control for scalable video coding extension of the H.264/AVC. [Citation Graph (, )][DBLP]

  461. Optimal rate allocation for scalable video multicast over WiMAX. [Citation Graph (, )][DBLP]

  462. Software implementation of Chien search process for strong BCH codes. [Citation Graph (, )][DBLP]

  463. Structured LDPCcodes with low error floor based on PEG tanner graphs. [Citation Graph (, )][DBLP]

  464. Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range. [Citation Graph (, )][DBLP]

  465. Back-illuminated ultraviolet image sensor in silicon-on-sapphire. [Citation Graph (, )][DBLP]

  466. CMOS image sensor readout employing in-pixel transistor current sensing. [Citation Graph (, )][DBLP]

  467. Image sensor with focal plane change event driven video compression. [Citation Graph (, )][DBLP]

  468. A low-power CMOS front end for particle detection applications. [Citation Graph (, )][DBLP]

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  472. On low power design of feedforward continuous-time sigma delta modulators with excess loop delay. [Citation Graph (, )][DBLP]

  473. Fixed-step simulation of Continuous-Time SigmaDelta modulators. [Citation Graph (, )][DBLP]

  474. Design of error-tolerant cache memory for multithreaded computing. [Citation Graph (, )][DBLP]

  475. Dynamic wordline voltage swing for low leakage and stable static memory banks. [Citation Graph (, )][DBLP]

  476. Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. [Citation Graph (, )][DBLP]

  477. PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion. [Citation Graph (, )][DBLP]

  478. A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. [Citation Graph (, )][DBLP]

  479. An efficient finite precision realization of the block adaptive decision feedback equalizer. [Citation Graph (, )][DBLP]

  480. Bit-level optimized FIR filter architectures for high-speed decimation applications. [Citation Graph (, )][DBLP]

  481. Prediction of protein-coding regions in DNA sequences using a model-based approach. [Citation Graph (, )][DBLP]

  482. An area-efficient sampling rate converter using negative feedback technique. [Citation Graph (, )][DBLP]

  483. Thermo-visual video fusion using probabilistic graphical model for human tracking. [Citation Graph (, )][DBLP]

  484. A programmable dual hysteretic window comparator. [Citation Graph (, )][DBLP]

  485. A simple and accurate method to predict offset voltage in dynamic comparators. [Citation Graph (, )][DBLP]

  486. Adjustable hysteresis CMOS Schmitt triggers. [Citation Graph (, )][DBLP]

  487. Low-current consumption CMOS comparator using charge-storage amplifier for A/D converters. [Citation Graph (, )][DBLP]

  488. Low-power static and dynamic high-voltage CMOS level-shifter circuits. [Citation Graph (, )][DBLP]

  489. 700MHz RF transceiver of base station for 802.16e. [Citation Graph (, )][DBLP]

  490. A 200Mbps 0.02nJ/b dual-mode inductive coupling transceiver for cm-range interconnection. [Citation Graph (, )][DBLP]

  491. 0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power. [Citation Graph (, )][DBLP]

  492. A charge pump-based direct frequency modulator. [Citation Graph (, )][DBLP]

  493. Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. [Citation Graph (, )][DBLP]

  494. An implantable I-UWB transceiver architecture with power carrier synchronization. [Citation Graph (, )][DBLP]

  495. A low-power silicon-on-sapphire tunable ultra-wideband transmitter. [Citation Graph (, )][DBLP]

  496. A reconfigurable IC for wireless monitoring of chemical or electrical neural activity. [Citation Graph (, )][DBLP]

  497. Tracking tongue movements for environment control using particle swarm optimization. [Citation Graph (, )][DBLP]

  498. A brain-machine interface using dry-contact, low-noise EEG sensors. [Citation Graph (, )][DBLP]

  499. Chemical and biological sensors for environmental monitoring. [Citation Graph (, )][DBLP]

  500. A mobile environmental sensing system to manage transportation and urban air quality. [Citation Graph (, )][DBLP]

  501. Genetically-engineered whole-cell bioreporters on integrated circuits for environmental monitoring. [Citation Graph (, )][DBLP]

  502. Baseline resistance cancellation circuit for high resolution thiolate-monolayer-protected gold nanoparticle vapor sensor arrays. [Citation Graph (, )][DBLP]

  503. A multiplexed biosensor based on biomolecular nanowires. [Citation Graph (, )][DBLP]

  504. Cost-effective and low-power memory address bus encodings. [Citation Graph (, )][DBLP]

  505. Logic synthesis method for FPGAs with embedded memory blocks. [Citation Graph (, )][DBLP]

  506. Concurrent skew and control step assignments in RT-level datapath synthesis. [Citation Graph (, )][DBLP]

  507. Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. [Citation Graph (, )][DBLP]

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  509. Seizure detection on prolonged-EEG videos. [Citation Graph (, )][DBLP]

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  511. Analog CMOS charge model for molecular redox electron-transfer reactions and bio-chemical pathways. [Citation Graph (, )][DBLP]

  512. Data scaling in remote health monitoring systems. [Citation Graph (, )][DBLP]

  513. State estimation for a model of gene expression. [Citation Graph (, )][DBLP]

  514. A multi-hypothesis decoder for multiple description video coding. [Citation Graph (, )][DBLP]

  515. Probabilistic prefetching scheme for P2P VoD applications with frequent seeks. [Citation Graph (, )][DBLP]

  516. An optimized link adaptation scheme for efficient delivery of scalable H.264 Video over IEEE 802.11n. [Citation Graph (, )][DBLP]

  517. Robust video multicast with joint network coding and AL-FEC. [Citation Graph (, )][DBLP]

  518. A hierarchical push-pull scheme for peer-to-peer live streaming. [Citation Graph (, )][DBLP]

  519. A cluster-based computing infrastructure for wide-area multi-modal surveillance networks. [Citation Graph (, )][DBLP]

  520. A sensor placement algorithm for redundant covering based on Riesz energy minimization. [Citation Graph (, )][DBLP]

  521. An adaptive ISFET chemical imager chip. [Citation Graph (, )][DBLP]

  522. A 0.35µm 1.25V piezo-resistance digital ROIC for liquid dispensing MEMS. [Citation Graph (, )][DBLP]

  523. MEMS automotive collision avoidence radar beamformer. [Citation Graph (, )][DBLP]

  524. Design of reliable interface system for eddy current displacement sensors in vacuum environments1. [Citation Graph (, )][DBLP]

  525. A low noise CMOS preamplifier for femtoampere current detection. [Citation Graph (, )][DBLP]

  526. A low power CMOS sigma-delta readout circuit for heterogeneously integrated chemoresistive micro-/nano- sensor arrays. [Citation Graph (, )][DBLP]

  527. Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems. [Citation Graph (, )][DBLP]

  528. A piezoelectric actuator driver circuit for automatic focusing of mobile phone cameras. [Citation Graph (, )][DBLP]

  529. Binaural spectral cues for ultrasonic localization. [Citation Graph (, )][DBLP]

  530. Optimum camera placement considering camera specification for security monitoring. [Citation Graph (, )][DBLP]

  531. Position, damping and inertia control of parallel-plate electrostatic actuators. [Citation Graph (, )][DBLP]

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  533. A Time Domain differential CMOS Temperature Sensor with Reduced Supply Sensitivity. [Citation Graph (, )][DBLP]

  534. An asynchronous time-based image sensor. [Citation Graph (, )][DBLP]

  535. A CMOS image sensor with focal plane SPIHT image compression. [Citation Graph (, )][DBLP]

  536. Autonomous CMOS image sensor for real time target detection and tracking. [Citation Graph (, )][DBLP]

  537. Low power linear current mode imager with 1.5 transistors per pixel. [Citation Graph (, )][DBLP]

  538. Two color asynchronous event photo pixel. [Citation Graph (, )][DBLP]

  539. High-speed character recognition system based on a complex hierarchical AER architecture. [Citation Graph (, )][DBLP]

  540. Temporally learning floating-gate VLSI synapses. [Citation Graph (, )][DBLP]

  541. A novel CMOS current mode fully differential tanh (x) implementation. [Citation Graph (, )][DBLP]

  542. Implementing a neuromorphic cross-correlation engine with silicon neurons. [Citation Graph (, )][DBLP]

  543. Stability analysis for impulsive neural networks with variable delays. [Citation Graph (, )][DBLP]

  544. An averaging method for a committee of special-orthogonal-group machines. [Citation Graph (, )][DBLP]

  545. CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. [Citation Graph (, )][DBLP]

  546. An E-nose haar wavelet preprocessing circuit for spiking neural network classification. [Citation Graph (, )][DBLP]

  547. Adaptive delay compensation in multi-dithering adaptive control. [Citation Graph (, )][DBLP]

  548. Delta-sigma modulated class D ZCS series resonant inverter with an inductive load. [Citation Graph (, )][DBLP]

  549. Design of class DE amplifier with nonlinear shunt capacitances for any output Q. [Citation Graph (, )][DBLP]

  550. A novel current controlled tri-state boost converter with superior dynamic performance. [Citation Graph (, )][DBLP]

  551. Low-OSR asynchronous Sigma-Delta modulation high-order buck converter for efficient wideband switching amplification. [Citation Graph (, )][DBLP]

  552. LED drivers with PPD compensation for achieving fast transient response. [Citation Graph (, )][DBLP]

  553. A quasi fixed frequency constant on time controlled boost converter. [Citation Graph (, )][DBLP]

  554. An asynchronous finite state machine controller for integrated buck-boost power converters in wideband signal-tracking applications. [Citation Graph (, )][DBLP]

  555. Zero current detection technique for fast transient response in buck DC-DC converters. [Citation Graph (, )][DBLP]

  556. Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications. [Citation Graph (, )][DBLP]

  557. Review of digital control laws for high-frequency point-of-load converters. [Citation Graph (, )][DBLP]

  558. An offset compensation technique for bandgap voltage reference in CMOS technology. [Citation Graph (, )][DBLP]

  559. Temperature performance of sub-1V ultra-low power current sources. [Citation Graph (, )][DBLP]

  560. A 1V power supply operation CMOS subbandgap reference using switched capacitors. [Citation Graph (, )][DBLP]

  561. A current limiter for LDO regulators with internal compensation for process and temperature variations. [Citation Graph (, )][DBLP]

  562. A high precision, output-capacitor-free low-dropout regulator for system-on-chip design. [Citation Graph (, )][DBLP]

  563. A parallel sampling scheme for ultra-wideband signal based on the random projection. [Citation Graph (, )][DBLP]

  564. A novel flash analog-to-digital converter. [Citation Graph (, )][DBLP]

  565. An M-2M digital-to-analog converter design methodology based on a physical mismatch model. [Citation Graph (, )][DBLP]

  566. Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback. [Citation Graph (, )][DBLP]

  567. Design of a 6 bit 1.25 GS/s DAC for WPAN. [Citation Graph (, )][DBLP]

  568. A CMOS 2.0-11.2 GHz UWB LNA using active inductor circuit. [Citation Graph (, )][DBLP]

  569. A novel topology in reversed nested miller compensation using dual-active capacitance. [Citation Graph (, )][DBLP]

  570. A low-voltage low-power fully differential rail-to-rail input/output opamp in 65-nm CMOS. [Citation Graph (, )][DBLP]

  571. Efficient four-stage frequency compensation for low-voltage amplifiers. [Citation Graph (, )][DBLP]

  572. A gain-enhancing technique for very low-voltage amplifiers. [Citation Graph (, )][DBLP]

  573. Diagnosis of assembly failures for System-in-Package RF tuners. [Citation Graph (, )][DBLP]

  574. Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems. [Citation Graph (, )][DBLP]

  575. Mixed-signal flexible architecture for the synthesis of n-port networks. [Citation Graph (, )][DBLP]

  576. A metastability-independent time-to-voltage converter. [Citation Graph (, )][DBLP]

  577. A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage. [Citation Graph (, )][DBLP]

  578. An improved method of power control with CMOS class-E power amplifiers. [Citation Graph (, )][DBLP]

  579. Programmable voltage-to-current converter with linear voltage control resistor. [Citation Graph (, )][DBLP]

  580. A highly accurate BiCMOS cascode current mirror for wide output voltage range. [Citation Graph (, )][DBLP]

  581. A 1.5V, wide-input range, high-bandwidth, CMOS four-quadrant analog multiplier. [Citation Graph (, )][DBLP]

  582. Synchronization of two LC- oscillators using capacitive coupling. [Citation Graph (, )][DBLP]

  583. Power and area efficient circular-memory switched-capacitor FIR baseband filter for WCDMA/GSM. [Citation Graph (, )][DBLP]

  584. 10GBase-LX4 optical fiber receiver in a 0.18µm digital CMOS process. [Citation Graph (, )][DBLP]

  585. Exponential-enhanced characteristic of MOS transistors and its application to log-domain circuits. [Citation Graph (, )][DBLP]

  586. Nyquist-rate analog-to-digital converter specification for Zero-IF UMTS receiver. [Citation Graph (, )][DBLP]

  587. Anticipatory access pipeline design for phased cache. [Citation Graph (, )][DBLP]

  588. An Analytical model for characteristic impedance in nanostrip plasmonic waveguides. [Citation Graph (, )][DBLP]

  589. A novel contribution to the RTD-based threshold logic family. [Citation Graph (, )][DBLP]

  590. Integration time optimization for integrating photosensors. [Citation Graph (, )][DBLP]

  591. A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. [Citation Graph (, )][DBLP]

  592. Low-power 50% duty cycle corrector. [Citation Graph (, )][DBLP]

  593. An inductively tuned CMOS astable multivibrator. [Citation Graph (, )][DBLP]

  594. Implementation of compact VLSI FitzHugh-Nagumo neurons. [Citation Graph (, )][DBLP]

  595. A CMOS realization of double-scroll chaotic circuit and its application to random number generation. [Citation Graph (, )][DBLP]

  596. Digital filtering for power amplifiers linearization. [Citation Graph (, )][DBLP]

  597. Long-term jitter reduction through supply noise compensation. [Citation Graph (, )][DBLP]

  598. Distortion calculation of an asynchronous switching xDSL line-driver. [Citation Graph (, )][DBLP]

  599. A novel multiscroll chaotic system and its realization. [Citation Graph (, )][DBLP]

  600. Investigation of state transition phenomena in cross-coupled chaotic circuits. [Citation Graph (, )][DBLP]

  601. Methods to eliminate dynamic errors in high-performance SAR A/D converter. [Citation Graph (, )][DBLP]

  602. System identification -based reduced-code testing for pipeline ADCs' linearity test. [Citation Graph (, )][DBLP]

  603. A fully digital ADC using a new delay element with enhanced linearity. [Citation Graph (, )][DBLP]

  604. Jitter error spectrum for NRZ D/A converters. [Citation Graph (, )][DBLP]

  605. Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators. [Citation Graph (, )][DBLP]

  606. Power-supply-variation-aware timing analysis of synchronous systems. [Citation Graph (, )][DBLP]

  607. Equivalent rise time for resonance in power/ground noise estimation. [Citation Graph (, )][DBLP]

  608. Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. [Citation Graph (, )][DBLP]

  609. Delay macromodeling and estimation for RTL. [Citation Graph (, )][DBLP]

  610. Time diversity approach for intra-chip RF/wireless interconnect systems. [Citation Graph (, )][DBLP]

  611. Complexity reduction for frequency-response masking filters using serial masking. [Citation Graph (, )][DBLP]

  612. Design of frequency-response-masking FIR filters using SOCP with coefficient sensitivity constraint. [Citation Graph (, )][DBLP]

  613. Subexpression encoded extrapolated impulse response FIR filter with perfect residual compensation. [Citation Graph (, )][DBLP]

  614. Hilbert transformers with a piecewise-polynomial-sinusoidal impulse response. [Citation Graph (, )][DBLP]

  615. Minimax IIR digital filter design using SOCP. [Citation Graph (, )][DBLP]

  616. CMOS ASIC for MHz silicon BAW gyroscope. [Citation Graph (, )][DBLP]

  617. An integrated design for the front-end of an inductive position sensor. [Citation Graph (, )][DBLP]

  618. The design of a chopped current-feedback instrumentation amplifier. [Citation Graph (, )][DBLP]

  619. Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems. [Citation Graph (, )][DBLP]

  620. A micropower front-end interface for differential-capacitive sensor systems. [Citation Graph (, )][DBLP]

  621. Frequency offset compensation for OFDM receiver using rotating concyclic antenna. [Citation Graph (, )][DBLP]

  622. IQ imbalance and phase noise mitigation for wireless OFDM systems. [Citation Graph (, )][DBLP]

  623. A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. [Citation Graph (, )][DBLP]

  624. Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. [Citation Graph (, )][DBLP]

  625. Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver. [Citation Graph (, )][DBLP]

  626. A novel safety system concept and implementation for implantable stimulators: A universal DC tissue leakage current detector. [Citation Graph (, )][DBLP]

  627. A high-output-impedance current microstimulator for anatomical rewiring of cortical circuitry. [Citation Graph (, )][DBLP]

  628. A partial-current-steering biphasic stimulation driver for neural prostheses. [Citation Graph (, )][DBLP]

  629. Extended counting ADC for 32-channel neural recording headstage for small animals. [Citation Graph (, )][DBLP]

  630. A back telemetry-capable active high efficiency rectifier in standard CMOS process. [Citation Graph (, )][DBLP]

  631. A brief overview of some recent advances in complex dynamical networks control and synchronization. [Citation Graph (, )][DBLP]

  632. Reducing synchronization cost in weighted dynamical networks using betweenness centrality measures. [Citation Graph (, )][DBLP]

  633. Vertex-based adaptive synchronization of complex networks. [Citation Graph (, )][DBLP]

  634. Localization of effective pinning control in complex networks of dynamical systems. [Citation Graph (, )][DBLP]

  635. The emergence of stable cooperators in heterogeneous networked systems. [Citation Graph (, )][DBLP]

  636. Phase noise in frequency divider circuits. [Citation Graph (, )][DBLP]

  637. ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. [Citation Graph (, )][DBLP]

  638. Post-optimization of Delta-Sigma modulators considering circuit non-idealities. [Citation Graph (, )][DBLP]

  639. A multi-step P-cell for LNA design automation. [Citation Graph (, )][DBLP]

  640. Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop. [Citation Graph (, )][DBLP]

  641. Low-voltage circuit design for widespread sensing applications. [Citation Graph (, )][DBLP]

  642. Ultra-low-power UWB for sensor network applications. [Citation Graph (, )][DBLP]

  643. System design considerations for sensor network applications. [Citation Graph (, )][DBLP]

  644. An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting. [Citation Graph (, )][DBLP]

  645. Circuit techniques for ultra-low power subthreshold SRAMs. [Citation Graph (, )][DBLP]

  646. Architectural analyses of K-Means silicon intellectual property for image segmentation. [Citation Graph (, )][DBLP]

  647. A sparse representation of physical activity video in the study of obesity. [Citation Graph (, )][DBLP]

  648. An efficient embedded compression algorithm using adjusted binary code method. [Citation Graph (, )][DBLP]

  649. Graph cut video object segmentation using histogram of oriented gradients. [Citation Graph (, )][DBLP]

  650. A high-quality spatial-temporal content-adaptive deinterlacing algorithm. [Citation Graph (, )][DBLP]

  651. High-bandwidth floating gate CMOS rectifiers with reduced voltage drop. [Citation Graph (, )][DBLP]

  652. A current mode adaptive on-time control scheme for fast transient DC-DC converters. [Citation Graph (, )][DBLP]

  653. Inductor-current zero-crossing detection mixed-signal CMOS circuit for a DCM-operated 3-level switching power converter. [Citation Graph (, )][DBLP]

  654. An integrated reconfigurable switched-capacitor DC-DC converter with a dual-loop adaptive gain-pulse control. [Citation Graph (, )][DBLP]

  655. Adaptive step-size digital controller for switching frequency auto-tuning. [Citation Graph (, )][DBLP]

  656. Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology. [Citation Graph (, )][DBLP]

  657. A reconfigurable direct RF receiver architecture. [Citation Graph (, )][DBLP]

  658. Fast frequency acquisition all-digital PLL using PVT calibration. [Citation Graph (, )][DBLP]

  659. A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation. [Citation Graph (, )][DBLP]

  660. A buffered charge pump with zero charge sharing. [Citation Graph (, )][DBLP]

  661. Don't care filling for power minimization in VLSI circuit testing. [Citation Graph (, )][DBLP]

  662. Design and analysis of skewed-distribution scan chain partition for improved test data compression. [Citation Graph (, )][DBLP]

  663. Intellectual property authentication by watermarking scan chain in design-for-testability flow. [Citation Graph (, )][DBLP]

  664. High performance data acquisition system for IRFPA testing. [Citation Graph (, )][DBLP]

  665. A fault-aware dynamic routing algorithm for on-chip networks. [Citation Graph (, )][DBLP]

  666. Generalized structure for designing odd-order variable fractional-delay filters. [Citation Graph (, )][DBLP]

  667. Design of discrete Fractional Hilbert transformer in time domain. [Citation Graph (, )][DBLP]

  668. The design of asymmetrical square-root pulse-shaping filters with wide eye-openings. [Citation Graph (, )][DBLP]

  669. Digital filter realizations absent of self-sustained oscillations. [Citation Graph (, )][DBLP]

  670. Improved hot-spot location technique for proteins using a bandpass notch digital filter. [Citation Graph (, )][DBLP]

  671. A capacitor-less low-dropout regulator for SoC with bi-directional asymmetric buffer. [Citation Graph (, )][DBLP]

  672. Low-voltage LDO Compensation Strategy based on Current Amplifiers. [Citation Graph (, )][DBLP]

  673. A low-voltage CMOS low-dropout regulator with novel capacitor-multiplier frequency compensation. [Citation Graph (, )][DBLP]

  674. High linear voltage references for on-chip CMOS smart temperature sensor from -60degreeC to 140degreeC. [Citation Graph (, )][DBLP]

  675. A low voltage CMOS bandgap reference circuit. [Citation Graph (, )][DBLP]

  676. A low-power mixing DAC IR-UWB-receiver. [Citation Graph (, )][DBLP]

  677. Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET. [Citation Graph (, )][DBLP]

  678. An energy-detector for non-coherent impulse-radio UWB receivers. [Citation Graph (, )][DBLP]

  679. The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications. [Citation Graph (, )][DBLP]

  680. A CMOS variable width short-pulse generator circuit for UWB RADAR applications. [Citation Graph (, )][DBLP]

  681. Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition. [Citation Graph (, )][DBLP]

  682. A 0.65V rail-to-rail constant gm opamp for biomedical applications. [Citation Graph (, )][DBLP]

  683. A 1-V 1.1-muW sensor interface IC for wearable biomedical devices. [Citation Graph (, )][DBLP]

  684. A DC coupled signal acquisition system with ultra-wide input range. [Citation Graph (, )][DBLP]

  685. An ultra low-power CMOS action potential detector. [Citation Graph (, )][DBLP]

  686. Human activity recognition for video surveillance. [Citation Graph (, )][DBLP]

  687. An experimental study on pedestrian classification using local features. [Citation Graph (, )][DBLP]

  688. A framework ofspatio-temporal analysisfor video surveillance. [Citation Graph (, )][DBLP]

  689. Multi-strategy object tracking in complex situation for video surveillance. [Citation Graph (, )][DBLP]

  690. A region-based object tracking scheme using Adaboost-based feature selection. [Citation Graph (, )][DBLP]

  691. Transient simulation of on-chip transmission lines via exact pole extraction. [Citation Graph (, )][DBLP]

  692. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]

  693. 3-D thermal simulation with dynamic power profiles. [Citation Graph (, )][DBLP]

  694. Leakage power optimization for clock network using dual-Vth technology. [Citation Graph (, )][DBLP]

  695. Binning algorithm for accurate computer aided device modeling. [Citation Graph (, )][DBLP]

  696. Novel interconnect infrastructures for massive multicore chips - an overview. [Citation Graph (, )][DBLP]

  697. Performance comparison between copper, carbon nanotube, and optical interconnects. [Citation Graph (, )][DBLP]

  698. Non-traditional irregular interconnects for massive scale SoC. [Citation Graph (, )][DBLP]

  699. Photonic networks-on-chip: Opportunities and challenges. [Citation Graph (, )][DBLP]

  700. Improving the scalability of checkpoint recovery for networks-on-chip. [Citation Graph (, )][DBLP]

  701. System level design of a spatio-temporal video resampling architecture. [Citation Graph (, )][DBLP]

  702. High efficiency architecture of escot with pass concurrent context modeling scheme for scalable video coding. [Citation Graph (, )][DBLP]

  703. An efficient VLSI architecture for rate disdortion optimization in AVS video encoder. [Citation Graph (, )][DBLP]

  704. Performance evaluation of DCT and wavelet transform for LSI. [Citation Graph (, )][DBLP]

  705. A transform, lighting and setup ASIC for surface splatting. [Citation Graph (, )][DBLP]

  706. A new state estimation using synchronized phasor measurements. [Citation Graph (, )][DBLP]

  707. Oscillation monitoring from ambient PMU measurements by Frequency Domain Decomposition. [Citation Graph (, )][DBLP]

  708. A thermal equivalent circuit for PEM fuel cell temperature control design. [Citation Graph (, )][DBLP]

  709. Fast-scale period-doubling bifurcation in voltage-mode controlled full-bridge inverter. [Citation Graph (, )][DBLP]

  710. An interleaved class E2 dc/dc converter. [Citation Graph (, )][DBLP]

  711. A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces. [Citation Graph (, )][DBLP]

  712. A highly linear CMOS current-controlled oscillator using a novel frequency detector. [Citation Graph (, )][DBLP]

  713. Programmable spread spectrum clock generation based on successive phase selection technique. [Citation Graph (, )][DBLP]

  714. A noise-shaping SC sine-wave oscillator. [Citation Graph (, )][DBLP]

  715. 7-decades tunable translinear SiGe BiCMOS 3-phase sinusoidal oscillator. [Citation Graph (, )][DBLP]

  716. A low-area interconnect architecture for chip multiprocessors. [Citation Graph (, )][DBLP]

  717. A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects. [Citation Graph (, )][DBLP]

  718. Explicit energy evaluation in RLC tree circuits with ramp inputs. [Citation Graph (, )][DBLP]

  719. Dynamic compact thermal model of a package. [Citation Graph (, )][DBLP]

  720. Modeling and simulation of complex heterogeneous systems. [Citation Graph (, )][DBLP]

  721. Local computation and estimation of wavelet coefficients in the dual-tree complex wavelet transform. [Citation Graph (, )][DBLP]

  722. A new structure of lifting wavelet for reducing rounding error. [Citation Graph (, )][DBLP]

  723. Statistical image modeling using von Mises distribution in the complex directional wavelet domain. [Citation Graph (, )][DBLP]

  724. On the probability density function of the derotated phase of complex wavelet coefficients. [Citation Graph (, )][DBLP]

  725. Introduction to the Discrete Shapelet Transform and a new paradigm: Joint time-frequency-shape analysis. [Citation Graph (, )][DBLP]

  726. A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs. [Citation Graph (, )][DBLP]

  727. Design and realization of continuous-time wave digital filters. [Citation Graph (, )][DBLP]

  728. Harmonic vs. geometric mean Sinh integrators in weak inversion CMOS. [Citation Graph (, )][DBLP]

  729. A PVT independent subthreshold constant-Gm stage for very low frequency applications. [Citation Graph (, )][DBLP]

  730. Design procedure for DVB-T receivers large tuning range LP filter. [Citation Graph (, )][DBLP]

  731. ASIC hardware implementations for 512-bit hash function Whirlpool. [Citation Graph (, )][DBLP]

  732. Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection. [Citation Graph (, )][DBLP]

  733. High-performance ASIC implementations of the 128-bit block cipher CLEFIA. [Citation Graph (, )][DBLP]

  734. Secure pseudo-random bit sequence generation using coupled linear congruential generators. [Citation Graph (, )][DBLP]

  735. Differential Power Analysis of a SHACAL-2 hardware implementation. [Citation Graph (, )][DBLP]

  736. Recursive Least Squares adaptive filters for ultrasonic signal deconvolution. [Citation Graph (, )][DBLP]

  737. Adaptive EMG neutralization using the modified QT. [Citation Graph (, )][DBLP]

  738. A low-distortion and wide dynamic range CMOS imager for wireless capsule endoscopy. [Citation Graph (, )][DBLP]

  739. New digital quadrature demodulator for real-time hand-held ultrasound medical imaging device. [Citation Graph (, )][DBLP]

  740. A real-time setup for multisite signal recording and processing in living neural networks. [Citation Graph (, )][DBLP]

  741. Multipurpose watermarking based on curvelet transform. [Citation Graph (, )][DBLP]

  742. Advanced colluder detection techniques for OSIFT-based hiding codes. [Citation Graph (, )][DBLP]

  743. Quality-aware GSM speech watermarking. [Citation Graph (, )][DBLP]

  744. Watermarking curves using 2D mesh spectral transform. [Citation Graph (, )][DBLP]

  745. An interactive and secure user authentication scheme for mobile devices. [Citation Graph (, )][DBLP]

  746. Stochastic model and simulation of a random number generator circuit. [Citation Graph (, )][DBLP]

  747. A fast band matching technique for impedance extraction. [Citation Graph (, )][DBLP]

  748. A novel approach to statistical simulation of ICS affected by non-linear variabilities. [Citation Graph (, )][DBLP]

  749. Process variations aware robust on-chip bus architecture synthesis for MPSoCs. [Citation Graph (, )][DBLP]

  750. Efficient linear macromodeling via least-squares response approximation. [Citation Graph (, )][DBLP]

  751. Sigma-delta learning for super-resolution independent component analysis. [Citation Graph (, )][DBLP]

  752. Fast blind equalization with two-stage single/multilevel modulus and DD algorithm for high order QAM cable systems. [Citation Graph (, )][DBLP]

  753. Local independent component analysis applied to highly segmented detectors. [Citation Graph (, )][DBLP]

  754. Multiple-target localization and estimation of MIMO radars with unknown transmitted signals. [Citation Graph (, )][DBLP]

  755. Signal modulus design for blind source separation via algebraic known modulus algorithm: A perturbation perspective. [Citation Graph (, )][DBLP]

  756. Automatic video diagnosing method using embedded crypto-watermarks. [Citation Graph (, )][DBLP]

  757. Joint optimization of data hiding and video compression. [Citation Graph (, )][DBLP]

  758. Data hiding in inter and intra prediction modes of H.264/AVC. [Citation Graph (, )][DBLP]

  759. JPEG image steganalysis utilizing both intrablock and interblock correlations. [Citation Graph (, )][DBLP]

  760. A wavelet-based semi-fragile watermarking with recovery mechanism. [Citation Graph (, )][DBLP]

  761. Accelerated state-variable modeling of synchronous machine-converter systems. [Citation Graph (, )][DBLP]

  762. Sectionalized PWM (S-PWM): A new multilevel modulation strategy. [Citation Graph (, )][DBLP]

  763. Current mode DC-DC buck converters with optimal fast-transient control. [Citation Graph (, )][DBLP]

  764. On the design of single-inductor multiple-output DC-DC buck converters. [Citation Graph (, )][DBLP]

  765. Automatic dead-time adjustment CMOS mixed-signal circuit for a DCM-operated 3-level switching power converter. [Citation Graph (, )][DBLP]

  766. An 8 Mbps data rate transmission by inductive link dedicated to implantable devices. [Citation Graph (, )][DBLP]

  767. Design of an active-inductor-based termination circuit for high-speed I/O. [Citation Graph (, )][DBLP]

  768. A passive filter aided timing recovery scheme. [Citation Graph (, )][DBLP]

  769. A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O. [Citation Graph (, )][DBLP]

  770. Pulse-mode link for robust, high speed communications. [Citation Graph (, )][DBLP]

  771. Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. [Citation Graph (, )][DBLP]

  772. Symbol and carrier frequency offset synchronization for IEEE802.16e. [Citation Graph (, )][DBLP]

  773. A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. [Citation Graph (, )][DBLP]

  774. A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. [Citation Graph (, )][DBLP]

  775. CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. [Citation Graph (, )][DBLP]

  776. Adaptive equalization for filter bank based multicarrier systems. [Citation Graph (, )][DBLP]

  777. A new blind-block reciprocal parametric transform. [Citation Graph (, )][DBLP]

  778. A lattice structure for linear-phase perfect reconstruction filter banks with mirror image symmetric frequency response. [Citation Graph (, )][DBLP]

  779. Oversampled linear-phase perfect reconstruction filter banks with higher-order feasible building blocks: Structure and parameterization. [Citation Graph (, )][DBLP]

  780. A farrow-structure-based multi-mode transmultiplexer. [Citation Graph (, )][DBLP]

  781. Linear-enhanced V to I converters based on MOS resistive source degeneration. [Citation Graph (, )][DBLP]

  782. Log-domain channel-select filters for multistandard wireless receivers. [Citation Graph (, )][DBLP]

  783. Power and area efficient high speed analog adaptive equalization. [Citation Graph (, )][DBLP]

  784. Current-mode filter in 65nm CMOS for a software-radio application. [Citation Graph (, )][DBLP]

  785. Active bandpass filter using transformer feedback in 0.18-µm CMOS for 802.11a wireless LAN. [Citation Graph (, )][DBLP]

  786. A high SFDR direct digital synthesizer with frequency error free output. [Citation Graph (, )][DBLP]

  787. Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths. [Citation Graph (, )][DBLP]

  788. Design and low-power implementation of an adaptive image rejection receiver. [Citation Graph (, )][DBLP]

  789. Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. [Citation Graph (, )][DBLP]

  790. Efficient FPGA implementation of complex multipliers using the logarithmic number system. [Citation Graph (, )][DBLP]

  791. An ultra-low-power micro-optoelectromechanical tilt sensor. [Citation Graph (, )][DBLP]

  792. Polarization analyzing CMOS sensor for microchamber/microfluidic system based on image sensor technology. [Citation Graph (, )][DBLP]

  793. The chemical current-conveyor: a new microchip biosensor. [Citation Graph (, )][DBLP]

  794. A novel hybrid active-passive pixel with correlated double sampling CMOS readout circuit for medical x-ray imaging. [Citation Graph (, )][DBLP]

  795. A mini-invasive multi-function bladder urine pressure measurement system. [Citation Graph (, )][DBLP]

  796. Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits. [Citation Graph (, )][DBLP]

  797. Utilizing sub-threshold technology for the creation of secure circuits. [Citation Graph (, )][DBLP]

  798. Brand and IP protection with physical unclonable functions. [Citation Graph (, )][DBLP]

  799. Asynchronous balanced gates tolerant to interconnect variability. [Citation Graph (, )][DBLP]

  800. Physical unclonable function with tristate buffers. [Citation Graph (, )][DBLP]

  801. A least-squares based method for IIR filtering with noisy input-output data. [Citation Graph (, )][DBLP]

  802. An algorithm for ARMA model parameter estimation from noisy observations. [Citation Graph (, )][DBLP]

  803. An efficient approach for designing filter banks for Multi-Carrier Transmission. [Citation Graph (, )][DBLP]

  804. Adaptive wavelet denoising system for speech enhancement. [Citation Graph (, )][DBLP]

  805. Robust adaptive beamformers with linear matrix inequality constraints. [Citation Graph (, )][DBLP]

  806. Missing feature speech recognition in a meeting situation with maximum SNR beamforming. [Citation Graph (, )][DBLP]

  807. Multimicrophone speech dereverberation using spatiotemporal and spectral processing. [Citation Graph (, )][DBLP]

  808. Blind speech dereverberation using batch and sequential Monte Carlo methods. [Citation Graph (, )][DBLP]

  809. A study of identifibility for blind source separation via non-orthogonal joint diagonalization. [Citation Graph (, )][DBLP]

  810. Footstep classification using simple speech recognition technique. [Citation Graph (, )][DBLP]

  811. Audio event classification using binary hierarchical classifiers with feature selection for healthcare applications. [Citation Graph (, )][DBLP]

  812. Face hallucination based on independent component analysis. [Citation Graph (, )][DBLP]

  813. Face clustering in videos using constraint propagation. [Citation Graph (, )][DBLP]

  814. Musical beat tracking via Kalman filtering and noisy measurements selection. [Citation Graph (, )][DBLP]

  815. Efficient music representation with content adaptive dictionaries. [Citation Graph (, )][DBLP]

  816. ZVS operating frequency versus duty ratio of class E amplifier with nonlinear shunt capacitance. [Citation Graph (, )][DBLP]

  817. Characterizing fast-scale instability in a buck-based switching amplifier for wideband tracking. [Citation Graph (, )][DBLP]

  818. Smooth transition and ripple reduction in 4-switch non-inverting buck-boost power converter for WCDMA RF power amplifier. [Citation Graph (, )][DBLP]

  819. Off-time prediction in digital constant on-time modulation for DC-DC converters. [Citation Graph (, )][DBLP]

  820. A 2.5MHz, 97%-accuracy on-chip current sensor with dynamically-biased shunt feedback for current-mode switching DC-DC converters. [Citation Graph (, )][DBLP]

  821. A high speed word level finite field multiplier using reordered normal basis. [Citation Graph (, )][DBLP]

  822. Enhanced power analysis attack using chosen message against RSA hardware implementations. [Citation Graph (, )][DBLP]

  823. Advanced Encryption Standard (AES) implementation with increased DPA resistance and low overhead. [Citation Graph (, )][DBLP]

  824. On the security of a class of image encryption schemes. [Citation Graph (, )][DBLP]

  825. Implementation of AES S-Boxes using combinational logic. [Citation Graph (, )][DBLP]

  826. A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit. [Citation Graph (, )][DBLP]

  827. A full-custom design of AES SubByte module with signal independent power consumption. [Citation Graph (, )][DBLP]

  828. Switching activity reduction in low power Booth multiplier. [Citation Graph (, )][DBLP]

  829. A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor. [Citation Graph (, )][DBLP]

  830. Differential Power Analysis resistant hardware implementation of the RSA cryptosystem. [Citation Graph (, )][DBLP]

  831. A low-power monolithically stacked 3D-TCAM. [Citation Graph (, )][DBLP]

  832. "Green" micro-architecture and circuit co-design for ternary content addressable memory. [Citation Graph (, )][DBLP]

  833. A dynamic address decode circuit for implementing range addressable look-up tables. [Citation Graph (, )][DBLP]

  834. High speed single-ended pseudo differential current sense amplifier for SRAM cell. [Citation Graph (, )][DBLP]

  835. A nano-CMOS process variation induced read failure tolerant SRAM cell. [Citation Graph (, )][DBLP]

  836. A power-aware 2-dimensional bypassing multiplier using cell-based design flow. [Citation Graph (, )][DBLP]

  837. A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. [Citation Graph (, )][DBLP]

  838. A general model for differential power analysis attacks to static logic circuits. [Citation Graph (, )][DBLP]

  839. Programmable threshold voltage using quantum dot transistors for low-power mobile computing. [Citation Graph (, )][DBLP]

  840. A novel floating gate circuit family with subthreshold voltage swing for ultra-low power operation. [Citation Graph (, )][DBLP]

  841. A novel VLSI iterative divider architecture for fast quotient generation. [Citation Graph (, )][DBLP]

  842. Modified CSD group multiplier design for predetermined coefficient groups. [Citation Graph (, )][DBLP]

  843. New designs of Redundant-Binary full Adders and its applications. [Citation Graph (, )][DBLP]

  844. A variant of a radix-10 combinational multiplier. [Citation Graph (, )][DBLP]

  845. Reduced Z-datapath Cordic Rotator. [Citation Graph (, )][DBLP]

  846. A hybrid self-testing methodology of processor cores. [Citation Graph (, )][DBLP]

  847. PrSoC: Programmable System-on-chip (SoC) for silicon prototyping. [Citation Graph (, )][DBLP]

  848. Optimization technique for flip-flop inserted global interconnect. [Citation Graph (, )][DBLP]

  849. A real-time image denoising chip. [Citation Graph (, )][DBLP]

  850. Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. [Citation Graph (, )][DBLP]

  851. A semi-custom memory design for an asynchronous 8051 microcontroller. [Citation Graph (, )][DBLP]

  852. De-synchronization of a point-of-sales digital-logic controller. [Citation Graph (, )][DBLP]

  853. A cost effective reconfigurable memory for multimedia multithreading streaming architecture. [Citation Graph (, )][DBLP]

  854. A synchronized variable frequency clock scheme in chip multiprocessors. [Citation Graph (, )][DBLP]

  855. Full waveform accuracy to estimate delay in coupled digital circuits. [Citation Graph (, )][DBLP]

  856. Optimization of active circuits for substrate noise suppression. [Citation Graph (, )][DBLP]

  857. Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. [Citation Graph (, )][DBLP]

  858. A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. [Citation Graph (, )][DBLP]

  859. A data traffic efficient H.264 deblocking IP. [Citation Graph (, )][DBLP]

  860. ADAPTO: full-adder based reconfigurable architecture for bit level operations. [Citation Graph (, )][DBLP]

  861. Improving datapathutilization of programmable DSP with composite functional units. [Citation Graph (, )][DBLP]

  862. Bit-depth scalable coding based on macroblock level inter-layer prediction. [Citation Graph (, )][DBLP]

  863. Freeview rendering with trinocular camera. [Citation Graph (, )][DBLP]

  864. Side information generation with constrained relaxation for distributed multi-view video coding. [Citation Graph (, )][DBLP]

  865. Hyperspectral image coding with LVQ-SPECK. [Citation Graph (, )][DBLP]

  866. Wavelet based distributed video coding with spatial scalability. [Citation Graph (, )][DBLP]

  867. A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder. [Citation Graph (, )][DBLP]

  868. Enhanced temporal error concealment algorithm with edge-sensitive processing order. [Citation Graph (, )][DBLP]

  869. Frame loss error concealment for multiview video coding. [Citation Graph (, )][DBLP]

  870. Numerical error analysis for super-resolution reconstruction. [Citation Graph (, )][DBLP]

  871. ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision. [Citation Graph (, )][DBLP]

  872. Fast sub-pixel motion estimation and mode decision for H.264. [Citation Graph (, )][DBLP]

  873. Efficient all-zero block detection algorithm for H.264 integer transform. [Citation Graph (, )][DBLP]

  874. A novel fine rate control algorithm with adaptive rounding offset. [Citation Graph (, )][DBLP]

  875. Accelerating vector quantization of images using modified run length coding for adaptive block representation and difference measurement. [Citation Graph (, )][DBLP]

  876. Constant distortion rate control for H.264/AVC high definition videos with scene change. [Citation Graph (, )][DBLP]

  877. Fast selective-intra mode search algorithm based on macro-block tracking for inter-frames in the H.264/AVC video standard. [Citation Graph (, )][DBLP]

  878. Data Reuse method between Heterogeneous Partitions (DRHP) in H.264/AVC motion compensator. [Citation Graph (, )][DBLP]

  879. Performance evaluation of H.264 video over ad hoc networks based on dual mode IEEE 802.11B/G and EDCA MAC architecture. [Citation Graph (, )][DBLP]

  880. Overcoming burst packet loss in peer-to-peer live streaming systems. [Citation Graph (, )][DBLP]

  881. An SDRAM controller optimized for high definition video coding application. [Citation Graph (, )][DBLP]

  882. A baseball exploration system using spatial pattern recognition. [Citation Graph (, )][DBLP]

  883. Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception. [Citation Graph (, )][DBLP]

  884. Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems. [Citation Graph (, )][DBLP]

  885. Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm. [Citation Graph (, )][DBLP]

  886. A statistical framework for replay detection in soccer video. [Citation Graph (, )][DBLP]

  887. Advanced real time fire detection in video surveillance system. [Citation Graph (, )][DBLP]

  888. Suspicious object detection using fuzzy-color histogram. [Citation Graph (, )][DBLP]

  889. Video enhancement based on saturation adjustment and contrast enhancement. [Citation Graph (, )][DBLP]

  890. Algorithm for parallel inverse halftoning using partitioning of Look-Up Table (LUT). [Citation Graph (, )][DBLP]

  891. A feature-based image registration technique for images of different scale. [Citation Graph (, )][DBLP]

  892. Recover image coding loss with LMS filtering. [Citation Graph (, )][DBLP]

  893. FMO slice group maps using spatial and temporal indicators for H.264 wireless video transmission. [Citation Graph (, )][DBLP]

  894. Fast mode selection to reduce the encoding complexity of H.264/AVC. [Citation Graph (, )][DBLP]

  895. A generalized fast motion estimation algorithm using external and internal stop search techniques for H.264 video coding standard. [Citation Graph (, )][DBLP]

  896. Redundant multiscale structure coding for error resilient video completion. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002