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Conferences in DBLP
Nanotechnology for low-power and high-speed nanoelectronics applications. [Citation Graph (, )][DBLP]
Compact modeling of carbon nanotube transistor for early stage process-design exploration. [Citation Graph (, )][DBLP]
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. [Citation Graph (, )][DBLP]
Low power FPGA design using hybrid CMOS-NEMS approach. [Citation Graph (, )][DBLP]
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. [Citation Graph (, )][DBLP]
Clocking structures and power analysis for nanomagnet-based logic devices. [Citation Graph (, )][DBLP]
Energy efficient near-threshold chip multi-processing. [Citation Graph (, )][DBLP]
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. [Citation Graph (, )][DBLP]
Evaluating design tradeoffs in on-chip power management for CMPs. [Citation Graph (, )][DBLP]
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. [Citation Graph (, )][DBLP]
A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches. [Citation Graph (, )][DBLP]
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. [Citation Graph (, )][DBLP]
A robust edge encoding technique for energy-efficient multi-cycle interconnect. [Citation Graph (, )][DBLP]
Low-power process-variation tolerant arithmetic units using input-based elastic clocking. [Citation Graph (, )][DBLP]
Sleep transistor sizing and control for resonant supply noise damping. [Citation Graph (, )][DBLP]
Thermal-aware methodology for repeater insertion in low-power VLSI circuits. [Citation Graph (, )][DBLP]
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. [Citation Graph (, )][DBLP]
Power optimal MTCMOS repeater insertion for global buses. [Citation Graph (, )][DBLP]
Timing-driven row-based power gating. [Citation Graph (, )][DBLP]
Detailed placement for leakage reduction using systematic through-pitch variation. [Citation Graph (, )][DBLP]
Early power grid verification under circuit current uncertainties. [Citation Graph (, )][DBLP]
Future of on-chip interconnection architectures. [Citation Graph (, )][DBLP]
Towards a software approach to mitigate voltage emergencies. [Citation Graph (, )][DBLP]
Improving disk reuse for reducing power consumption. [Citation Graph (, )][DBLP]
PVS: passive voltage scaling for wireless sensor networks. [Citation Graph (, )][DBLP]
A programming environment with runtime energy characterization for energy-aware applications. [Citation Graph (, )][DBLP]
A process variation aware low power synthesis methodology for fixed-point FIR filters. [Citation Graph (, )][DBLP]
Voltage- and ABB-island optimization in high level synthesis. [Citation Graph (, )][DBLP]
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies. [Citation Graph (, )][DBLP]
Power signal processing: a new perspective for power analysis and optimization. [Citation Graph (, )][DBLP]
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. [Citation Graph (, )][DBLP]
A low-power SRAM using bit-line charge-recycling technique. [Citation Graph (, )][DBLP]
Minimizing power dissipation during write operation to register files. [Citation Graph (, )][DBLP]
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. [Citation Graph (, )][DBLP]
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. [Citation Graph (, )][DBLP]
Throughput of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]
Dynamic voltage frequency scaling for multi-tasking systems using online learning. [Citation Graph (, )][DBLP]
Thermal-aware task scheduling at the system software level. [Citation Graph (, )][DBLP]
Thermal response to DVFS: analysis with an Intel Pentium M. [Citation Graph (, )][DBLP]
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. [Citation Graph (, )][DBLP]
The parallel computing landscape: a Berkeley view. [Citation Graph (, )][DBLP]
Low power soft-output signal detector design for wireless MIMO communication systems. [Citation Graph (, )][DBLP]
A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices. [Citation Graph (, )][DBLP]
An architecture for energy efficient sphere decoding. [Citation Graph (, )][DBLP]
On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing. [Citation Graph (, )][DBLP]
Low-power H.264/AVC baseline decoder for portable applications. [Citation Graph (, )][DBLP]
A 0.4-V UWB baseband processor. [Citation Graph (, )][DBLP]
Resource area dilation to reduce power density in throughput servers. [Citation Graph (, )][DBLP]
Locality-driven architectural cache sub-banking for leakage energy reduction. [Citation Graph (, )][DBLP]
A multi-model power estimation engine for accuracy optimization. [Citation Graph (, )][DBLP]
A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devices. [Citation Graph (, )][DBLP]
High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine control. [Citation Graph (, )][DBLP]
A micro power management system and maximum output power control for solar energy harvesting applications. [Citation Graph (, )][DBLP]
Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor. [Citation Graph (, )][DBLP]
Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system. [Citation Graph (, )][DBLP]
Vibration energy scavenging and management for ultra low power applications. [Citation Graph (, )][DBLP]
Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source. [Citation Graph (, )][DBLP]
Design of an efficient power delivery network in an soc to enable dynamic power management. [Citation Graph (, )][DBLP]
Energy-efficient and performance-enhanced disks using flash-memory cache. [Citation Graph (, )][DBLP]
SAPP: scalable and adaptable peak power management in nocs. [Citation Graph (, )][DBLP]
All watts considered. [Citation Graph (, )][DBLP]
A 65-nm pulsed latch with a single clocked transistor. [Citation Graph (, )][DBLP]
A methodology for analysis and verification of power gated circuits with correlated results. [Citation Graph (, )][DBLP]
Vt balancing and device sizing towards high yield of sub-threshold static logic gates. [Citation Graph (, )][DBLP]
Power-efficient LDPC code decoder architecture. [Citation Graph (, )][DBLP]
A low-power CSCD asynchronous viterbi decoder for wireless applications. [Citation Graph (, )][DBLP]
Reducing cache energy consumption by tag encoding in embedded processors. [Citation Graph (, )][DBLP]
On reducing energy-consumption by late-inserting instructions into the issue queue. [Citation Graph (, )][DBLP]
Power-aware operand delivery. [Citation Graph (, )][DBLP]
On the latency, energy and area of checkpointed, superscalar register alias tables. [Citation Graph (, )][DBLP]
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design. [Citation Graph (, )][DBLP]
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. [Citation Graph (, )][DBLP]
Electromigration and voltage drop aware power grid optimization for power gated ICs. [Citation Graph (, )][DBLP]
Reducing display power in DVS-enabled handheld systems. [Citation Graph (, )][DBLP]
Multicasting based topology generation and core mapping for a power efficient networks-on-chip. [Citation Graph (, )][DBLP]
Phase-aware adaptive hardware selection for power-efficient scientific computations. [Citation Graph (, )][DBLP]
Signoff power methodology for contactless smartcards. [Citation Graph (, )][DBLP]
An ilp based approach to reducing energy consumption in nocbased CMPS. [Citation Graph (, )][DBLP]
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