The Ternary Calculating Machine of Thomas Fowler. [Citation Graph (, )][DBLP]

Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore. [Citation Graph (, )][DBLP]

Automated Reasoning in Some Local Extensions of Ordered Structures. [Citation Graph (, )][DBLP]

Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule. [Citation Graph (, )][DBLP]

Model-Characterizing Formulas and Normal Forms in Godel Logics. [Citation Graph (, )][DBLP]

Spectral Analysis of Special Properties of Ternary Functions. [Citation Graph (, )][DBLP]

Representations of Elementary Functions Using Edge-Valued MDDs. [Citation Graph (, )][DBLP]

Experimental Studies on SAT-Based ATPG for Gate Delay Faults. [Citation Graph (, )][DBLP]

Polynomials as Generators of Minimal Clones. [Citation Graph (, )][DBLP]

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. [Citation Graph (, )][DBLP]

A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic. [Citation Graph (, )][DBLP]

The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons. [Citation Graph (, )][DBLP]

Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency. [Citation Graph (, )][DBLP]

New Fastest Linearly Independent Transforms over GF(3). [Citation Graph (, )][DBLP]

Inversion/Division in Galois Field Using Multiple-Valued Logic. [Citation Graph (, )][DBLP]

Boolean Functions of Low Polynomial Degree for Quantum Query Complexity Theory. [Citation Graph (, )][DBLP]

Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions. [Citation Graph (, )][DBLP]

Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic. [Citation Graph (, )][DBLP]

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. [Citation Graph (, )][DBLP]

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. [Citation Graph (, )][DBLP]

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. [Citation Graph (, )][DBLP]

On the Axiomatization of Generalized Entropic Metrics. [Citation Graph (, )][DBLP]

Characterization of Partial Sheffer Functions in 3-Valued Logic. [Citation Graph (, )][DBLP]

Power Indexes in Voting Systems and Multiple-Valued Logic. [Citation Graph (, )][DBLP]

A Ternary Analog-to-Digital Converter System. [Citation Graph (, )][DBLP]

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. [Citation Graph (, )][DBLP]

An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays. [Citation Graph (, )][DBLP]

Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum. [Citation Graph (, )][DBLP]

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. [Citation Graph (, )][DBLP]

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. [Citation Graph (, )][DBLP]

Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. [Citation Graph (, )][DBLP]

Classifications and Enumeration of Bases in P_{3}(2). [Citation Graph (, )][DBLP]

Simulation of Gate Circuits with Feedback in Multi-Valued Algebras. [Citation Graph (, )][DBLP]

Properties and Fast Algorithms for Ternary Walsh Transform. [Citation Graph (, )][DBLP]

Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. [Citation Graph (, )][DBLP]

Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. [Citation Graph (, )][DBLP]

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. [Citation Graph (, )][DBLP]

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. [Citation Graph (, )][DBLP]

Evaluation and Comparison of Threshold Logic Gates. [Citation Graph (, )][DBLP]

Towards First-Order Symbolic Trajectory Evaluation. [Citation Graph (, )][DBLP]

Survey of Stochastic Computation on Factor Graphs. [Citation Graph (, )][DBLP]

A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms. [Citation Graph (, )][DBLP]