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Conferences in DBLP

IEEE International Symposium on Multiple-Valued Logic (ISMVL) (ismvl)
2007 (conf/ismvl/2007)

  1. The Ternary Calculating Machine of Thomas Fowler. [Citation Graph (, )][DBLP]

  2. Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore. [Citation Graph (, )][DBLP]

  3. Automated Reasoning in Some Local Extensions of Ordered Structures. [Citation Graph (, )][DBLP]

  4. Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule. [Citation Graph (, )][DBLP]

  5. Model-Characterizing Formulas and Normal Forms in Godel Logics. [Citation Graph (, )][DBLP]

  6. Spectral Analysis of Special Properties of Ternary Functions. [Citation Graph (, )][DBLP]

  7. Representations of Elementary Functions Using Edge-Valued MDDs. [Citation Graph (, )][DBLP]

  8. Experimental Studies on SAT-Based ATPG for Gate Delay Faults. [Citation Graph (, )][DBLP]

  9. Polynomials as Generators of Minimal Clones. [Citation Graph (, )][DBLP]

  10. Restriction-Closed Hyperclones. [Citation Graph (, )][DBLP]

  11. Monoidal Intervals of Partial Clones. [Citation Graph (, )][DBLP]

  12. Variable Reordering and Sifting for QMDD. [Citation Graph (, )][DBLP]

  13. GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. [Citation Graph (, )][DBLP]

  14. A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic. [Citation Graph (, )][DBLP]

  15. The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons. [Citation Graph (, )][DBLP]

  16. Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency. [Citation Graph (, )][DBLP]

  17. New Fastest Linearly Independent Transforms over GF(3). [Citation Graph (, )][DBLP]

  18. Inversion/Division in Galois Field Using Multiple-Valued Logic. [Citation Graph (, )][DBLP]

  19. Boolean Functions of Low Polynomial Degree for Quantum Query Complexity Theory. [Citation Graph (, )][DBLP]

  20. Quantum Robots for Teenagers. [Citation Graph (, )][DBLP]

  21. Quantum Mechanical Model of Emotional Robot Behaviors. [Citation Graph (, )][DBLP]

  22. Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates. [Citation Graph (, )][DBLP]

  23. 2-SAT Problems in Some Multi-Valued Logics Based on Finite Lattices. [Citation Graph (, )][DBLP]

  24. A Complete Resolution Calculus for Signed Max-SAT. [Citation Graph (, )][DBLP]

  25. Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions. [Citation Graph (, )][DBLP]

  26. Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. [Citation Graph (, )][DBLP]

  27. Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. [Citation Graph (, )][DBLP]

  28. Equalization Techniques for Multiple-Valued Data Transmission and Their Application. [Citation Graph (, )][DBLP]

  29. The Rough Powerset Monad. [Citation Graph (, )][DBLP]

  30. Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions. [Citation Graph (, )][DBLP]

  31. Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic. [Citation Graph (, )][DBLP]

  32. Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. [Citation Graph (, )][DBLP]

  33. Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. [Citation Graph (, )][DBLP]

  34. On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. [Citation Graph (, )][DBLP]

  35. On the Axiomatization of Generalized Entropic Metrics. [Citation Graph (, )][DBLP]

  36. Characterization of Partial Sheffer Functions in 3-Valued Logic. [Citation Graph (, )][DBLP]

  37. Power Indexes in Voting Systems and Multiple-Valued Logic. [Citation Graph (, )][DBLP]

  38. A Ternary Analog-to-Digital Converter System. [Citation Graph (, )][DBLP]

  39. Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices. [Citation Graph (, )][DBLP]

  40. Fault Tolerant CMOS Logic Using Ternary Gates. [Citation Graph (, )][DBLP]

  41. Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. [Citation Graph (, )][DBLP]

  42. An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays. [Citation Graph (, )][DBLP]

  43. Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum. [Citation Graph (, )][DBLP]

  44. Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. [Citation Graph (, )][DBLP]

  45. Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. [Citation Graph (, )][DBLP]

  46. Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. [Citation Graph (, )][DBLP]

  47. Classifications and Enumeration of Bases in P_{3}(2). [Citation Graph (, )][DBLP]

  48. Simulation of Gate Circuits with Feedback in Multi-Valued Algebras. [Citation Graph (, )][DBLP]

  49. Properties and Fast Algorithms for Ternary Walsh Transform. [Citation Graph (, )][DBLP]

  50. Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. [Citation Graph (, )][DBLP]

  51. Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. [Citation Graph (, )][DBLP]

  52. Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. [Citation Graph (, )][DBLP]

  53. Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. [Citation Graph (, )][DBLP]

  54. Evaluation and Comparison of Threshold Logic Gates. [Citation Graph (, )][DBLP]

  55. Towards First-Order Symbolic Trajectory Evaluation. [Citation Graph (, )][DBLP]

  56. Survey of Stochastic Computation on Factor Graphs. [Citation Graph (, )][DBLP]

  57. A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms. [Citation Graph (, )][DBLP]

  58. Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design. [Citation Graph (, )][DBLP]

  59. High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. [Citation Graph (, )][DBLP]

  60. Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process. [Citation Graph (, )][DBLP]

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