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Conferences in DBLP

IEEE International Symposium on Multiple-Valued Logic (ISMVL) (ismvl)
2008 (conf/ismvl/2008)

  1. EDA to the Rescue of the Silicon Roadmap. [Citation Graph (, )][DBLP]

  2. A Mature Methodology for Implementing Multi-Valued Logic in Silicon. [Citation Graph (, )][DBLP]

  3. Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. [Citation Graph (, )][DBLP]

  4. Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. [Citation Graph (, )][DBLP]

  5. Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data. [Citation Graph (, )][DBLP]

  6. Betweenness, Metrics and Entropies in Lattices. [Citation Graph (, )][DBLP]

  7. On Maximal Hyperclones on {0, 1} — A New Approach. [Citation Graph (, )][DBLP]

  8. Majority and Other Polynomials in Minimal Clones. [Citation Graph (, )][DBLP]

  9. Comparative Study by Solving the Test Compaction Problem. [Citation Graph (, )][DBLP]

  10. Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. [Citation Graph (, )][DBLP]

  11. On the Complexity of Classification Functions. [Citation Graph (, )][DBLP]

  12. MDD with Added Null-Value and All-Value Edges. [Citation Graph (, )][DBLP]

  13. High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. [Citation Graph (, )][DBLP]

  14. Permutations under Spectral Transforms. [Citation Graph (, )][DBLP]

  15. On Fixed Points and Cycles in the Reed Muller Domain. [Citation Graph (, )][DBLP]

  16. A Galois Field Approach to Modelling Gene Expression Regulation. [Citation Graph (, )][DBLP]

  17. On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. [Citation Graph (, )][DBLP]

  18. Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics. [Citation Graph (, )][DBLP]

  19. Encoding Max-CSP into Partial Max-SAT. [Citation Graph (, )][DBLP]

  20. High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. [Citation Graph (, )][DBLP]

  21. Semirigid Equivalence Relations on a Finite Set. [Citation Graph (, )][DBLP]

  22. Foundations of Higher Radix Numeric Computation. [Citation Graph (, )][DBLP]

  23. Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram. [Citation Graph (, )][DBLP]

  24. A Qualitative Modal Representation of Quantum Register Transformations. [Citation Graph (, )][DBLP]

  25. On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. [Citation Graph (, )][DBLP]

  26. Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID). [Citation Graph (, )][DBLP]

  27. Generalized Modus Ponens Based on Linguistic Modifiers in a Symbolic Multi-Valued Framework. [Citation Graph (, )][DBLP]

  28. Soft Computing Methods for Prediction of Replication Origins in Caudoviruses. [Citation Graph (, )][DBLP]

  29. Default Reasoning with Imperfect Information in Multivalued Logics. [Citation Graph (, )][DBLP]

  30. Classification of Fastest Quaternary Linearly Independent Arithmetic Transforms. [Citation Graph (, )][DBLP]

  31. A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter. [Citation Graph (, )][DBLP]

  32. Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. [Citation Graph (, )][DBLP]

  33. Multiple Valued Logic Using 3-State Quantum Dot Gate FETs. [Citation Graph (, )][DBLP]

  34. Projective Measurement-Based Logic Synthesis of Quantum Circuits. [Citation Graph (, )][DBLP]

  35. Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells. [Citation Graph (, )][DBLP]

  36. Quantum Logic Implementation of Unary Arithmetic Operations. [Citation Graph (, )][DBLP]

  37. Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits. [Citation Graph (, )][DBLP]

  38. Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. [Citation Graph (, )][DBLP]

  39. RevLib: An Online Resource for Reversible Functions and Reversible Circuits. [Citation Graph (, )][DBLP]

  40. Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms. [Citation Graph (, )][DBLP]

  41. Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions. [Citation Graph (, )][DBLP]

  42. Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups. [Citation Graph (, )][DBLP]

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