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Conferences in DBLP

IEEE International Symposium on Multiple-Valued Logic (ISMVL) (ismvl)
2009 (conf/ismvl/2009)

  1. Counting Problems and Clones of Functions. [Citation Graph (, )][DBLP]

  2. Web-Based Nursing Care Quality Improvement System with Fuzzy Recommendation System. [Citation Graph (, )][DBLP]

  3. A Study of Practical Causality Acquisition among Vital Signals. [Citation Graph (, )][DBLP]

  4. Biometric System by Foot Pressure Change Based on Neural Network. [Citation Graph (, )][DBLP]

  5. Fuzzy Logic Assisted Quantification of Gyral Deformation Index Using Magnetic Resonance Images for the Infantile Brain. [Citation Graph (, )][DBLP]

  6. Fuzzy Rule Extraction from Nursing-Care Texts. [Citation Graph (, )][DBLP]

  7. Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. [Citation Graph (, )][DBLP]

  8. Optimization of Current-Mode MVD-ORNS Arithmetic Circuits. [Citation Graph (, )][DBLP]

  9. 16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin. [Citation Graph (, )][DBLP]

  10. Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. [Citation Graph (, )][DBLP]

  11. Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. [Citation Graph (, )][DBLP]

  12. Mining Approximative Descriptions of Sets Using Rough Sets. [Citation Graph (, )][DBLP]

  13. Positive Primitive Structures. [Citation Graph (, )][DBLP]

  14. Paradigms for Non-classical Substitutions. [Citation Graph (, )][DBLP]

  15. Bounding the Phase Transition on Edge Matching Puzzles. [Citation Graph (, )][DBLP]

  16. Efficient Implementation of Controlled Operations for Multivalued Quantum Logic. [Citation Graph (, )][DBLP]

  17. Quantum Finite State Machines as Sequential Quantum Circuits. [Citation Graph (, )][DBLP]

  18. Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output. [Citation Graph (, )][DBLP]

  19. Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input. [Citation Graph (, )][DBLP]

  20. Multi-valued Modal Fixed Point Logics for Model Checking. [Citation Graph (, )][DBLP]

  21. Minimal Coverings of Maximal Partial Clones. [Citation Graph (, )][DBLP]

  22. Frozen Boolean Partial Co-clones. [Citation Graph (, )][DBLP]

  23. The Minimal Covering of Maximal Partial Clones in 4-valued Logic. [Citation Graph (, )][DBLP]

  24. On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering. [Citation Graph (, )][DBLP]

  25. Design of a High-Speed Fuzzy Logic Controller Based on Log-Domain Arithmetic. [Citation Graph (, )][DBLP]

  26. The Use of Multiple Connected Pseudo Minterms in the Synthesis of MVL Functions. [Citation Graph (, )][DBLP]

  27. A Two-Pronged Approach of Power-Aware Voltage Scheduling for Real-Time Task Graphs in Multi-processor Systems. [Citation Graph (, )][DBLP]

  28. Computational Neuroscience and Multiple-Valued Logic. [Citation Graph (, )][DBLP]

  29. Hyperclones Determined by Total-Parts of Hyper-relations. [Citation Graph (, )][DBLP]

  30. On Endoprimal Monoids in Clone Theory. [Citation Graph (, )][DBLP]

  31. Partial Clones Containing All Selfdual Monotonic Boolean Partial Functions. [Citation Graph (, )][DBLP]

  32. On Periodic Patterns and their Spectra. [Citation Graph (, )][DBLP]

  33. Generalized Discrete Hartley Transforms. [Citation Graph (, )][DBLP]

  34. Generating Hard Instances for MaxSAT. [Citation Graph (, )][DBLP]

  35. Regular Encodings from Max-CSP into Partial Max-SAT. [Citation Graph (, )][DBLP]

  36. Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial). [Citation Graph (, )][DBLP]

  37. An Overview of a Software Tool in Rough Non-deterministic Information Analysis. [Citation Graph (, )][DBLP]

  38. On Decision Making under Interval Uncertainty: A New Justification of Hurwicz Optimism-Pessimism Approach and its Use in Group Decision Making. [Citation Graph (, )][DBLP]

  39. Optimization of Fuzzy If-Then Rule Bases by Evolutionary Tuning of the Operations. [Citation Graph (, )][DBLP]

  40. Non-convex Fuzzy Truth Values and De Morgan Bisemilattices. [Citation Graph (, )][DBLP]

  41. Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. [Citation Graph (, )][DBLP]

  42. Multiple-Valued Constant-Power Adder for Cryptographic Processors. [Citation Graph (, )][DBLP]

  43. Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders. [Citation Graph (, )][DBLP]

  44. Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects. [Citation Graph (, )][DBLP]

  45. Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. [Citation Graph (, )][DBLP]

  46. Multiple Valued Logic Algebra for the Synthesis of Digital Circuits. [Citation Graph (, )][DBLP]

  47. Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. [Citation Graph (, )][DBLP]

  48. Attribute Reduction as Calculation of Focus in Granular Reasoning. [Citation Graph (, )][DBLP]

  49. Clarifying the Systems of Axioms Based on the Method of Indeterminate Coefficients. [Citation Graph (, )][DBLP]

  50. Applying Rough Sets to Information Tables Containing Missing Values. [Citation Graph (, )][DBLP]

  51. Generalized Extended t-Norms as t-Norms of Type 2. [Citation Graph (, )][DBLP]

  52. Evaluation of Cardinality Constraints on SMT-Based Debugging. [Citation Graph (, )][DBLP]

  53. Application of Covering Codes for Reduced Representations of Logic Functions. [Citation Graph (, )][DBLP]

  54. Ternary Logic by 3rd Subharmonics and its Application to Multiway Switches. [Citation Graph (, )][DBLP]

  55. Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure. [Citation Graph (, )][DBLP]

  56. Equivalence Checking of Reversible Circuits. [Citation Graph (, )][DBLP]

  57. Multi-path Switching Device Utilizing a Multi-terminal Nanowire Junction for MDD-Based Logic Circuit. [Citation Graph (, )][DBLP]

  58. Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors. [Citation Graph (, )][DBLP]

  59. Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits. [Citation Graph (, )][DBLP]

  60. Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. [Citation Graph (, )][DBLP]

  61. Representing the Genetic Code as a Function on a Galois Field Using the Reed-Muller Expansion. [Citation Graph (, )][DBLP]

  62. A Quaternary Decision Diagram Machine and the Optimization of its Code. [Citation Graph (, )][DBLP]

  63. Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits. [Citation Graph (, )][DBLP]

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