Conferences in DBLP
(ispass) Accelerating architecture research. [Citation Graph (, )][DBLP ] Performance analysis in the real world of on line services. [Citation Graph (, )][DBLP ] Differentiating the roles of IR measurement and simulation for power and temperature-aware design. [Citation Graph (, )][DBLP ] User- and process-driven dynamic voltage and frequency scaling. [Citation Graph (, )][DBLP ] Accuracy of performance counter measurements. [Citation Graph (, )][DBLP ] GARNET: A detailed on-chip network model inside a full-system simulator. [Citation Graph (, )][DBLP ] Cetra: A trace and analysis framework for the evaluation of Cell BE systems. [Citation Graph (, )][DBLP ] Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. [Citation Graph (, )][DBLP ] Lonestar: A suite of parallel irregular programs. [Citation Graph (, )][DBLP ] Exploring speculative parallelism in SPEC2006. [Citation Graph (, )][DBLP ] Machine learning based online performance prediction for runtime parallelization and task scheduling. [Citation Graph (, )][DBLP ] WARP: Enabling fast CPU scheduler development and evaluation. [Citation Graph (, )][DBLP ] CMPSched$im: Evaluating OS/CMP interaction on shared cache management. [Citation Graph (, )][DBLP ] Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform. [Citation Graph (, )][DBLP ] The data-centricity of Web 2.0 workloads and its impact on server performance. [Citation Graph (, )][DBLP ] Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. [Citation Graph (, )][DBLP ] An analytic model of optimistic Software Transactional Memory. [Citation Graph (, )][DBLP ] Analyzing CUDA workloads using a detailed GPU simulator. [Citation Graph (, )][DBLP ] Evaluating GPUs for network packet signature matching. [Citation Graph (, )][DBLP ] Online compression of cache-filtered address traces. [Citation Graph (, )][DBLP ] Analysis of the TRIPS prototype block predictor. [Citation Graph (, )][DBLP ] Experiment flows and microbenchmarks for reverse engineering of branch predictor structures. [Citation Graph (, )][DBLP ] Analyzing the impact of on-chip network traffic on program phases for CMPs. [Citation Graph (, )][DBLP ] SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code. [Citation Graph (, )][DBLP ] Accurately approximating superscalar processor performance from traces. [Citation Graph (, )][DBLP ] QUICK: A flexible full-system functional model. [Citation Graph (, )][DBLP ] 