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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
2008 (conf/ispd/2008)


  1. Design or manufacturing: which will be best for the future of the semiconductor roadmap? [Citation Graph (, )][DBLP]


  2. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. [Citation Graph (, )][DBLP]


  3. Robust gate sizing via mean excess delay minimization. [Citation Graph (, )][DBLP]


  4. Multi-scenario buffer insertion in multi-core processor designs. [Citation Graph (, )][DBLP]


  5. Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. [Citation Graph (, )][DBLP]


  6. Metal-density driven placement for cmp variation and routability. [Citation Graph (, )][DBLP]


  7. Highly efficient gradient computation for density-constrained analytical placement methods. [Citation Graph (, )][DBLP]


  8. Abacus: fast legalization of standard cell circuits with minimal movement. [Citation Graph (, )][DBLP]


  9. 3-D floorplanning using labeled tree and dual sequences. [Citation Graph (, )][DBLP]


  10. Variations, margins, and statistics. [Citation Graph (, )][DBLP]


  11. Implications of device timing variability on full chip timing. [Citation Graph (, )][DBLP]


  12. How to get real mad. [Citation Graph (, )][DBLP]


  13. A robust approach to lithography friendly design implementation. [Citation Graph (, )][DBLP]


  14. Fast interconnect synthesis with layer assignment. [Citation Graph (, )][DBLP]


  15. RF interconnects for communications on-chip. [Citation Graph (, )][DBLP]


  16. Placement challenges for structured ASICs. [Citation Graph (, )][DBLP]


  17. A framework for layout-level logic restructuring. [Citation Graph (, )][DBLP]


  18. Optimizing non-monotonic interconnect using functional simulation and logic restructuring. [Citation Graph (, )][DBLP]


  19. Reap what you sow: spare cells for post-silicon metal fix. [Citation Graph (, )][DBLP]


  20. Optimal post-routing redundant via insertion. [Citation Graph (, )][DBLP]


  21. Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree. [Citation Graph (, )][DBLP]


  22. An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (, )][DBLP]


  23. Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. [Citation Graph (, )][DBLP]


  24. Issues in global routing. [Citation Graph (, )][DBLP]


  25. The coming of age of (academic) global routing. [Citation Graph (, )][DBLP]


  26. The ISPD global routing benchmark suite. [Citation Graph (, )][DBLP]


  27. Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. [Citation Graph (, )][DBLP]


  28. Stress aware layout optimization. [Citation Graph (, )][DBLP]


  29. Discrete buffer and wire sizing for link-based non-tree clock networks. [Citation Graph (, )][DBLP]


  30. Activity and register placement aware gated clock network design. [Citation Graph (, )][DBLP]


  31. Automated design of digital microfluidic lab-on-chip under pin-count constraints. [Citation Graph (, )][DBLP]


  32. Physical design issues in biofluidic microchips. [Citation Graph (, )][DBLP]


  33. A high-performance droplet router for digital microfluidic biochips. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002