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Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
2009 (conf/ispd/2009)

  1. One look into the future of CMOS chip design. [Citation Graph (, )][DBLP]

  2. Early analysis for power distribution networks. [Citation Graph (, )][DBLP]

  3. Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. [Citation Graph (, )][DBLP]

  4. Multi-voltage floorplan design with optimal voltage assignment. [Citation Graph (, )][DBLP]

  5. Robust interconnect communication capacity algorithm by geometric programming. [Citation Graph (, )][DBLP]

  6. A new algorithm for simultaneous gate sizing and threshold voltage assignment. [Citation Graph (, )][DBLP]

  7. On stress aware active area sizing, gate sizing, and repeater insertion. [Citation Graph (, )][DBLP]

  8. Fast buffering for optimizing worst slack and resource consumption in repeater trees. [Citation Graph (, )][DBLP]

  9. On improving optimization effectiveness in interconnect-driven physical synthesis. [Citation Graph (, )][DBLP]

  10. Will 22nm be our catch 22!: design and cad challenges. [Citation Graph (, )][DBLP]

  11. New strategies for gridded physical design for 32nm technologies and beyond. [Citation Graph (, )][DBLP]

  12. Vertical slit transistor based integrated circuits (VeSTICs) paradigm. [Citation Graph (, )][DBLP]

  13. Graphene based transistors: physics, status and future perspectives. [Citation Graph (, )][DBLP]

  14. Accelerated design of analog, mixed-signal circuits in Titan. [Citation Graph (, )][DBLP]

  15. Physical design methodology for analog circuitsin a system-on-a-chip environment. [Citation Graph (, )][DBLP]

  16. Constraint-driven design: the next step towards analog design automation. [Citation Graph (, )][DBLP]

  17. Transistor-level layout of high-density regular circuits. [Citation Graph (, )][DBLP]

  18. Physical optimization for FPGAs using post-placement topology rewriting. [Citation Graph (, )][DBLP]

  19. A routing approach to reduce glitches in low power FPGAs. [Citation Graph (, )][DBLP]

  20. Double patterning layout decomposition for simultaneous conflict and stitch minimization. [Citation Graph (, )][DBLP]

  21. An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization. [Citation Graph (, )][DBLP]

  22. Redundant via insertion with wire bending. [Citation Graph (, )][DBLP]

  23. Wire shaping is practical. [Citation Graph (, )][DBLP]

  24. Industrial clock design. [Citation Graph (, )][DBLP]

  25. An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. [Citation Graph (, )][DBLP]

  26. Ispd2009 clock network synthesis contest. [Citation Graph (, )][DBLP]

  27. Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. [Citation Graph (, )][DBLP]

  28. Robust layer assignment for via optimization in multi-layer global routing. [Citation Graph (, )][DBLP]

  29. A faster approximation scheme for timing driven minimum cost layer assignment. [Citation Graph (, )][DBLP]

  30. Diffusion-driven congestion reduction for substrate topological routing. [Citation Graph (, )][DBLP]

  31. The challenges of correlating silicon and models in high variability CMOS processes. [Citation Graph (, )][DBLP]

  32. Synthesizing a representative critical path for post-silicon delay prediction. [Citation Graph (, )][DBLP]

  33. A metal-only-ECO solver for input-slew and output-loading violations. [Citation Graph (, )][DBLP]

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