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Conferences in DBLP
Physical design of biological systems. [Citation Graph (, )][DBLP]
Going with the flow: bridging the gap between theory and practice in physical design. [Citation Graph (, )][DBLP]
Design planning trends and challenges. [Citation Graph (, )][DBLP]
What makes a design difficult to route. [Citation Graph (, )][DBLP]
Physical design challenges beyond the 22nm node. [Citation Graph (, )][DBLP]
Challenges and opportunities in optimization of automotive electronics. [Citation Graph (, )][DBLP]
Thinking outside of the chip. [Citation Graph (, )][DBLP]
B-escape: a simultaneous escape routing algorithm based on boundary routing. [Citation Graph (, )][DBLP]
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (, )][DBLP]
Completing high-quality global routes. [Citation Graph (, )][DBLP]
Analog layout synthesis: what's missing? [Citation Graph (, )][DBLP]
Design platform for electrical and physical co-design of analog circuits. [Citation Graph (, )][DBLP]
Automatic generation of hierarchical placement rules for analog integrated circuits. [Citation Graph (, )][DBLP]
Adding a new dimension to physical design. [Citation Graph (, )][DBLP]
Physical design implementation for 3D IC: methodology and tools. [Citation Graph (, )][DBLP]
Efficient design practices for thermal management of a TSV based 3D IC system. [Citation Graph (, )][DBLP]
An analytical placer for mixed-size 3D placement. [Citation Graph (, )][DBLP]
Logical and physical restructuring of fan-in trees. [Citation Graph (, )][DBLP]
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]
ITOP: integrating timing optimization within placement. [Citation Graph (, )][DBLP]
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. [Citation Graph (, )][DBLP]
Dummy fill optimization for enhanced manufacturability. [Citation Graph (, )][DBLP]
Density gradient minimization with coupling-constrained dummy fill for CMP control. [Citation Graph (, )][DBLP]
Total sensitivity based dfm optimization of standard library cells. [Citation Graph (, )][DBLP]
A matching based decomposer for double patterning lithography. [Citation Graph (, )][DBLP]
Skew management of NBTI impacted gated clock trees. [Citation Graph (, )][DBLP]
Accurate clock mesh sizing via sequential quadraticprogramming. [Citation Graph (, )][DBLP]
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. [Citation Graph (, )][DBLP]
Impact of local interconnects on timing and power in a high performance microprocessor. [Citation Graph (, )][DBLP]
Interconnect power and delay optimization by dynamic programming in gridded design rules. [Citation Graph (, )][DBLP]
Performance study of VeSFET-based, high-density regular circuits. [Citation Graph (, )][DBLP]
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems. [Citation Graph (, )][DBLP]
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. [Citation Graph (, )][DBLP]
SafeChoice: a novel clustering algorithm for wirelength-driven placement. [Citation Graph (, )][DBLP]
Droplet-routing-aware module placement for cross-referencing biochips. [Citation Graph (, )][DBLP]
A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. [Citation Graph (, )][DBLP]
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