Conferences in DBLP

International Symposium on Physical Design (ISPD) (ispd)
2010 (conf/ispd/2010)

1. 
   Physical design of biological systems. [Citation Graph (, )][DBLP]
   
   
2. 
   Going with the flow: bridging the gap between theory and practice in physical design. [Citation Graph (, )][DBLP]
   
   
3. 
   Design planning trends and challenges. [Citation Graph (, )][DBLP]
   
   
4. 
   What makes a design difficult to route. [Citation Graph (, )][DBLP]
   
   
5. 
   Physical design challenges beyond the 22nm node. [Citation Graph (, )][DBLP]
   
   
6. 
   Challenges and opportunities in optimization of automotive electronics. [Citation Graph (, )][DBLP]
   
   
7. 
   Thinking outside of the chip. [Citation Graph (, )][DBLP]
   
   
8. 
   B-escape: a simultaneous escape routing algorithm based on boundary routing. [Citation Graph (, )][DBLP]
   
   
9. 
   FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (, )][DBLP]
   
   
10. 
    Completing high-quality global routes. [Citation Graph (, )][DBLP]
    
    
11. 
    Analog layout synthesis: what's missing? [Citation Graph (, )][DBLP]
    
    
12. 
    Design platform for electrical and physical co-design of analog circuits. [Citation Graph (, )][DBLP]
    
    
13. 
    Automatic generation of hierarchical placement rules for analog integrated circuits. [Citation Graph (, )][DBLP]
    
    
14. 
    Adding a new dimension to physical design. [Citation Graph (, )][DBLP]
    
    
15. 
    Physical design implementation for 3D IC: methodology and tools. [Citation Graph (, )][DBLP]
    
    
16. 
    Efficient design practices for thermal management of a TSV based 3D IC system. [Citation Graph (, )][DBLP]
    
    
17. 
    An analytical placer for mixed-size 3D placement. [Citation Graph (, )][DBLP]
    
    
18. 
    Logical and physical restructuring of fan-in trees. [Citation Graph (, )][DBLP]
    
    
19. 
    Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]
    
    
20. 
    ITOP: integrating timing optimization within placement. [Citation Graph (, )][DBLP]
    
    
21. 
    Physical synthesis of bus matrix for high bandwidth low power on-chip communications. [Citation Graph (, )][DBLP]
    
    
22. 
    Dummy fill optimization for enhanced manufacturability. [Citation Graph (, )][DBLP]
    
    
23. 
    Density gradient minimization with coupling-constrained dummy fill for CMP control. [Citation Graph (, )][DBLP]
    
    
24. 
    Total sensitivity based dfm optimization of standard library cells. [Citation Graph (, )][DBLP]
    
    
25. 
    A matching based decomposer for double patterning lithography. [Citation Graph (, )][DBLP]
    
    
26. 
    Skew management of NBTI impacted gated clock trees. [Citation Graph (, )][DBLP]
    
    
27. 
    Accurate clock mesh sizing via sequential quadraticprogramming. [Citation Graph (, )][DBLP]
    
    
28. 
    ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. [Citation Graph (, )][DBLP]
    
    
29. 
    Impact of local interconnects on timing and power in a high performance microprocessor. [Citation Graph (, )][DBLP]
    
    
30. 
    Interconnect power and delay optimization by dynamic programming in gridded design rules. [Citation Graph (, )][DBLP]
    
    
31. 
    Performance study of VeSFET-based, high-density regular circuits. [Citation Graph (, )][DBLP]
    
    
32. 
    A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems. [Citation Graph (, )][DBLP]
    
    
33. 
    Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. [Citation Graph (, )][DBLP]
    
    
34. 
    SafeChoice: a novel clustering algorithm for wirelength-driven placement. [Citation Graph (, )][DBLP]
    
    
35. 
    Droplet-routing-aware module placement for cross-referencing biochips. [Citation Graph (, )][DBLP]
    
    
36. 
    A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. [Citation Graph (, )][DBLP]