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Conferences in DBLP

International Symposium on Quality Electronic Design (isqed)
2008 (conf/isqed/2008)


  1. Tutorial 1: The Promise of High-Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications. [Citation Graph (, )][DBLP]


  2. Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies. [Citation Graph (, )][DBLP]


  3. Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology. [Citation Graph (, )][DBLP]


  4. Tutorial 4: Robust System Design in Scaled CMOS. [Citation Graph (, )][DBLP]


  5. Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve? [Citation Graph (, )][DBLP]


  6. Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM). [Citation Graph (, )][DBLP]


  7. Plenary Speech 1P1: Shrinking time-to-market through global value chain integration. [Citation Graph (, )][DBLP]


  8. Plenary Speech 1P2: Bounding the Endless Verification Loop. [Citation Graph (, )][DBLP]


  9. A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS. [Citation Graph (, )][DBLP]


  10. Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation. [Citation Graph (, )][DBLP]


  11. Error Protected Data Bus Inversion Using Standard DRAM Components. [Citation Graph (, )][DBLP]


  12. Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. [Citation Graph (, )][DBLP]


  13. Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. [Citation Graph (, )][DBLP]


  14. Fast and Accurate Waveform Analysis with Current Source Models. [Citation Graph (, )][DBLP]


  15. An Efficient Method for Fast Delay and SI Calculation Using Current Source Models. [Citation Graph (, )][DBLP]


  16. Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model. [Citation Graph (, )][DBLP]


  17. Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. [Citation Graph (, )][DBLP]


  18. Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths. [Citation Graph (, )][DBLP]


  19. IR Drop Reduction via a Flip-Flop Resynthesis Technique. [Citation Graph (, )][DBLP]


  20. Noise Interaction Between Power Distribution Grids and Substrate. [Citation Graph (, )][DBLP]


  21. Luncheon Keynote Speech. [Citation Graph (, )][DBLP]


  22. Fundamental Data Retention Limits in SRAM Standby Experimental Results. [Citation Graph (, )][DBLP]


  23. Quality of a Bit (QoB): A New Concept in Dependable SRAM. [Citation Graph (, )][DBLP]


  24. Cache Design for Low Power and High Yield. [Citation Graph (, )][DBLP]


  25. Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations. [Citation Graph (, )][DBLP]


  26. High Output Resistance and Wide Swing Voltage Charge Pump Circuit. [Citation Graph (, )][DBLP]


  27. Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. [Citation Graph (, )][DBLP]


  28. A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. [Citation Graph (, )][DBLP]


  29. Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. [Citation Graph (, )][DBLP]


  30. Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. [Citation Graph (, )][DBLP]


  31. Accurate Temperature Estimation for Efficient Thermal Management. [Citation Graph (, )][DBLP]


  32. Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. [Citation Graph (, )][DBLP]


  33. Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. [Citation Graph (, )][DBLP]


  34. A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors. [Citation Graph (, )][DBLP]


  35. Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. [Citation Graph (, )][DBLP]


  36. Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. [Citation Graph (, )][DBLP]


  37. High-Quality Circuit Synthesis for Modern Technologies. [Citation Graph (, )][DBLP]


  38. ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis. [Citation Graph (, )][DBLP]


  39. Improving the Efficiency of Power Management Techniques by Using Bayesian Classification. [Citation Graph (, )][DBLP]


  40. An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. [Citation Graph (, )][DBLP]


  41. Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior. [Citation Graph (, )][DBLP]


  42. Thermal-Aware IR Drop Analysis in Large Power Grid. [Citation Graph (, )][DBLP]


  43. A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. [Citation Graph (, )][DBLP]


  44. Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. [Citation Graph (, )][DBLP]


  45. Characterization of Standard Cells for Intra-Cell Mismatch Variations. [Citation Graph (, )][DBLP]


  46. Full-Chip Leakage Verification for Manufacturing Considering Process Variations. [Citation Graph (, )][DBLP]


  47. Processor Verification with hwBugHunt. [Citation Graph (, )][DBLP]


  48. Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. [Citation Graph (, )][DBLP]


  49. Efficient Selection of Observation Points for Functional Tests. [Citation Graph (, )][DBLP]


  50. A Novel Test Generation Methodology for Adaptive Diagnosis. [Citation Graph (, )][DBLP]


  51. Timing-Aware Multiple-Delay-Fault Diagnosis. [Citation Graph (, )][DBLP]


  52. A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. [Citation Graph (, )][DBLP]


  53. Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. [Citation Graph (, )][DBLP]


  54. A Statistic-Based Approach to Testability Analysis. [Citation Graph (, )][DBLP]


  55. Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes. [Citation Graph (, )][DBLP]


  56. On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem. [Citation Graph (, )][DBLP]


  57. Architecting for Physical Verification Performance and Scaling. [Citation Graph (, )][DBLP]


  58. Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. [Citation Graph (, )][DBLP]


  59. CMOS Based Low Cost Temperature Sensor. [Citation Graph (, )][DBLP]


  60. An SSO Based Methodology for EM Emission Estimation from SoCs. [Citation Graph (, )][DBLP]


  61. Fast Timing Update under the Effect of IR Drop. [Citation Graph (, )][DBLP]


  62. Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. [Citation Graph (, )][DBLP]


  63. Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. [Citation Graph (, )][DBLP]


  64. A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. [Citation Graph (, )][DBLP]


  65. Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. [Citation Graph (, )][DBLP]


  66. Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies. [Citation Graph (, )][DBLP]


  67. Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. [Citation Graph (, )][DBLP]


  68. Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation. [Citation Graph (, )][DBLP]


  69. Hotspot Based Yield Prediction with Consideration of Correlations. [Citation Graph (, )][DBLP]


  70. A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications. [Citation Graph (, )][DBLP]


  71. A Passive 915 MHz UHF RFID Tag. [Citation Graph (, )][DBLP]


  72. Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. [Citation Graph (, )][DBLP]


  73. DFM Based Detailed Routing Algorithm for ECP and CMP. [Citation Graph (, )][DBLP]


  74. Instruction Scheduling for Variation-Originated Variable Latencies. [Citation Graph (, )][DBLP]


  75. Hotspot Prevention Using CMP Model in Design Implementation Flow. [Citation Graph (, )][DBLP]


  76. The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era. [Citation Graph (, )][DBLP]


  77. Computation of Waveform Sensitivity Using Geometric Transforms for SSTA. [Citation Graph (, )][DBLP]


  78. On Efficient and Robust Constraint Generation for Practical Layout Legalization. [Citation Graph (, )][DBLP]


  79. Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family. [Citation Graph (, )][DBLP]


  80. Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. [Citation Graph (, )][DBLP]


  81. Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs. [Citation Graph (, )][DBLP]


  82. Analytical Noise-Rejection Model Based on Short Channel MOSFET. [Citation Graph (, )][DBLP]


  83. A High-Performance Bus Architecture for Strongly Coupled Interconnects. [Citation Graph (, )][DBLP]


  84. A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. [Citation Graph (, )][DBLP]


  85. A Holistic Approach to SoC Verification. [Citation Graph (, )][DBLP]


  86. A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel’s Test Chips. [Citation Graph (, )][DBLP]


  87. Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices. [Citation Graph (, )][DBLP]


  88. Verification of IP-Core Based SoC's. [Citation Graph (, )][DBLP]


  89. Innovative Test Solutions for Pin-Limited Microcontrollers. [Citation Graph (, )][DBLP]


  90. XStatic: A Simulation Based ESD Verification and Debug Environment. [Citation Graph (, )][DBLP]


  91. Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping. [Citation Graph (, )][DBLP]


  92. Cell Swapping Based Migration Methodology for Analog and Custom Layouts. [Citation Graph (, )][DBLP]


  93. A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models. [Citation Graph (, )][DBLP]


  94. System Verilog for Quality of Results (QoR). [Citation Graph (, )][DBLP]


  95. Power Delivery System: Sufficiency, Efficiency, and Stability. [Citation Graph (, )][DBLP]


  96. Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. [Citation Graph (, )][DBLP]


  97. Clock Skew Analysis via Vector Fitting in Frequency Domain. [Citation Graph (, )][DBLP]


  98. An Approach for a Comprehensive QA Methodology for the PDKs. [Citation Graph (, )][DBLP]


  99. Strategies for Quality CAD PDKs. [Citation Graph (, )][DBLP]


  100. Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. [Citation Graph (, )][DBLP]


  101. Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. [Citation Graph (, )][DBLP]


  102. Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics. [Citation Graph (, )][DBLP]


  103. A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. [Citation Graph (, )][DBLP]


  104. Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. [Citation Graph (, )][DBLP]


  105. Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. [Citation Graph (, )][DBLP]


  106. Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. [Citation Graph (, )][DBLP]


  107. A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs. [Citation Graph (, )][DBLP]


  108. Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure. [Citation Graph (, )][DBLP]


  109. Elastic Timing Scheme for Energy-Efficient and Robust Performance. [Citation Graph (, )][DBLP]


  110. Statistical Models and Frequency-Dependent Corner Models for Passive Devices. [Citation Graph (, )][DBLP]


  111. A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. [Citation Graph (, )][DBLP]


  112. Analytical Model for the Propagation Delay of Through Silicon Vias. [Citation Graph (, )][DBLP]


  113. Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock. [Citation Graph (, )][DBLP]


  114. A QoS Scheduler for Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  115. FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver. [Citation Graph (, )][DBLP]


  116. A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. [Citation Graph (, )][DBLP]


  117. Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test. [Citation Graph (, )][DBLP]


  118. Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality. [Citation Graph (, )][DBLP]


  119. Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The World. [Citation Graph (, )][DBLP]


  120. System-in-Package Technology: Opportunities and Challenges. [Citation Graph (, )][DBLP]


  121. Printed Circuit Board Assembly Test Process and Design for Testability. [Citation Graph (, )][DBLP]


  122. Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages. [Citation Graph (, )][DBLP]


  123. An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. [Citation Graph (, )][DBLP]


  124. Techniques for Early Package Closure in System-in-Packages. [Citation Graph (, )][DBLP]


  125. Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. [Citation Graph (, )][DBLP]


  126. MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis. [Citation Graph (, )][DBLP]


  127. Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. [Citation Graph (, )][DBLP]


  128. Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. [Citation Graph (, )][DBLP]


  129. 2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. [Citation Graph (, )][DBLP]


  130. Automated Standard Cell Library Analysis for Improved Defect Modeling. [Citation Graph (, )][DBLP]


  131. A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. [Citation Graph (, )][DBLP]


  132. Finite-Point Gate Model for Fast Timing and Power Analysis. [Citation Graph (, )][DBLP]


  133. Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. [Citation Graph (, )][DBLP]


  134. Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces. [Citation Graph (, )][DBLP]


  135. Practical Clock Tree Robustness Signoff Metrics. [Citation Graph (, )][DBLP]


  136. Hierarchical Soft Error Estimation Tool (HSEET). [Citation Graph (, )][DBLP]


  137. Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). [Citation Graph (, )][DBLP]


  138. Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect. [Citation Graph (, )][DBLP]


  139. Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. [Citation Graph (, )][DBLP]


  140. Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. [Citation Graph (, )][DBLP]


  141. High Resolution Read-Out Circuit for DNA Label-Free Detection System. [Citation Graph (, )][DBLP]


  142. Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. [Citation Graph (, )][DBLP]


  143. Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. [Citation Graph (, )][DBLP]


  144. Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise. [Citation Graph (, )][DBLP]


  145. Process-Variation Statistical Modeling for VLSI Timing Analysis. [Citation Graph (, )][DBLP]


  146. A Design Model for Random Process Variability. [Citation Graph (, )][DBLP]


  147. A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm. [Citation Graph (, )][DBLP]


  148. Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform. [Citation Graph (, )][DBLP]


  149. Runtime Validation of Transactional Memory Systems. [Citation Graph (, )][DBLP]


  150. SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. [Citation Graph (, )][DBLP]


  151. Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect. [Citation Graph (, )][DBLP]


  152. An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. [Citation Graph (, )][DBLP]


  153. Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. [Citation Graph (, )][DBLP]


  154. Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  155. A Basis for Formal Robustness Checking. [Citation Graph (, )][DBLP]


  156. Quantified Impacts of Guardband Reduction on Design Process Outcomes. [Citation Graph (, )][DBLP]


  157. Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. [Citation Graph (, )][DBLP]


  158. A Root-Finding Method for Assessing SRAM Stability. [Citation Graph (, )][DBLP]


  159. Cellwise OPC Based on Reduced Standard Cell Library. [Citation Graph (, )][DBLP]


  160. On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. [Citation Graph (, )][DBLP]


  161. Interval Based X-Masking for Scan Compression Architectures. [Citation Graph (, )][DBLP]


  162. Two New Methods for Accurate Test Set Relaxation via Test Set Replacement. [Citation Graph (, )][DBLP]


  163. Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. [Citation Graph (, )][DBLP]


  164. A Built-in Test and Characterization Method for Circuit Marginality Related Failures. [Citation Graph (, )][DBLP]


  165. On Chip Jitter Measurement through a High Accuracy TDC. [Citation Graph (, )][DBLP]


  166. Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas. [Citation Graph (, )][DBLP]


  167. Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. [Citation Graph (, )][DBLP]


  168. Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. [Citation Graph (, )][DBLP]


  169. Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method. [Citation Graph (, )][DBLP]


  170. IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. [Citation Graph (, )][DBLP]

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