High Output Resistance and Wide Swing Voltage Charge Pump Circuit. [Citation Graph (, )][DBLP]
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. [Citation Graph (, )][DBLP]
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. [Citation Graph (, )][DBLP]
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. [Citation Graph (, )][DBLP]
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. [Citation Graph (, )][DBLP]
Accurate Temperature Estimation for Efficient Thermal Management. [Citation Graph (, )][DBLP]
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. [Citation Graph (, )][DBLP]
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. [Citation Graph (, )][DBLP]
A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors. [Citation Graph (, )][DBLP]
Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. [Citation Graph (, )][DBLP]
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. [Citation Graph (, )][DBLP]
High-Quality Circuit Synthesis for Modern Technologies. [Citation Graph (, )][DBLP]
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis. [Citation Graph (, )][DBLP]
Improving the Efficiency of Power Management Techniques by Using Bayesian Classification. [Citation Graph (, )][DBLP]
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. [Citation Graph (, )][DBLP]
Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior. [Citation Graph (, )][DBLP]
Thermal-Aware IR Drop Analysis in Large Power Grid. [Citation Graph (, )][DBLP]
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. [Citation Graph (, )][DBLP]
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. [Citation Graph (, )][DBLP]
Characterization of Standard Cells for Intra-Cell Mismatch Variations. [Citation Graph (, )][DBLP]
Full-Chip Leakage Verification for Manufacturing Considering Process Variations. [Citation Graph (, )][DBLP]
An SSO Based Methodology for EM Emission Estimation from SoCs. [Citation Graph (, )][DBLP]
Fast Timing Update under the Effect of IR Drop. [Citation Graph (, )][DBLP]
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. [Citation Graph (, )][DBLP]
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. [Citation Graph (, )][DBLP]
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. [Citation Graph (, )][DBLP]
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. [Citation Graph (, )][DBLP]
Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies. [Citation Graph (, )][DBLP]
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. [Citation Graph (, )][DBLP]
Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation. [Citation Graph (, )][DBLP]
Hotspot Based Yield Prediction with Consideration of Correlations. [Citation Graph (, )][DBLP]
A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications. [Citation Graph (, )][DBLP]
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. [Citation Graph (, )][DBLP]
Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs. [Citation Graph (, )][DBLP]
Analytical Noise-Rejection Model Based on Short Channel MOSFET. [Citation Graph (, )][DBLP]
A High-Performance Bus Architecture for Strongly Coupled Interconnects. [Citation Graph (, )][DBLP]
A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. [Citation Graph (, )][DBLP]
Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform. [Citation Graph (, )][DBLP]
Runtime Validation of Transactional Memory Systems. [Citation Graph (, )][DBLP]
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. [Citation Graph (, )][DBLP]
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect. [Citation Graph (, )][DBLP]
An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. [Citation Graph (, )][DBLP]
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. [Citation Graph (, )][DBLP]