Conferences in DBLP

Annual Symposium on VLSI (isvlsi)
2008 (conf/isvlsi/2008)

1. 
   Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. [Citation Graph (, )][DBLP]
   
   
2. 
   Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories. [Citation Graph (, )][DBLP]
   
   
3. 
   Arithmetic Data Path Optimization Using Borrow-Save Representation. [Citation Graph (, )][DBLP]
   
   
4. 
   Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design. [Citation Graph (, )][DBLP]
   
   
5. 
   Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. [Citation Graph (, )][DBLP]
   
   
6. 
   Determining the Optimal Number of Islands in Power Islands Synthesis. [Citation Graph (, )][DBLP]
   
   
7. 
   Defect Tolerance Inspired by Artificial Evolution. [Citation Graph (, )][DBLP]
   
   
8. 
   Reliability of n-Bit Nanotechnology Adder. [Citation Graph (, )][DBLP]
   
   
9. 
   Spintronic Device Based Non-volatile Low Standby Power SRAM. [Citation Graph (, )][DBLP]
   
   
10. 
    Application of Bottom-Up Methodology to RTW VCO. [Citation Graph (, )][DBLP]
    
    
11. 
    A Closed-Loop Architecture with Digital Output for Convective Accelerometers. [Citation Graph (, )][DBLP]
    
    
12. 
    A CMOS Multi-sensor System for 3D Orientation Determination. [Citation Graph (, )][DBLP]
    
    
13. 
    FSMD Partitioning for Low Power Using ILP. [Citation Graph (, )][DBLP]
    
    
14. 
    Uncriticality-Directed Low-Power Instruction Scheduling. [Citation Graph (, )][DBLP]
    
    
15. 
    Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices. [Citation Graph (, )][DBLP]
    
    
16. 
    BTB Access Filtering: A Low Energy and High Performance Design. [Citation Graph (, )][DBLP]
    
    
17. 
    A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications. [Citation Graph (, )][DBLP]
    
    
18. 
    System Level Design Space Exploration for Multiprocessor System on Chip. [Citation Graph (, )][DBLP]
    
    
19. 
    A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures. [Citation Graph (, )][DBLP]
    
    
20. 
    MPI-Based Adaptive Task Migration Support on the HS-Scale System. [Citation Graph (, )][DBLP]
    
    
21. 
    Low Power High Performance Digitally Assisted Pipelined ADC. [Citation Graph (, )][DBLP]
    
    
22. 
    A Novel Low-Power Clock Skew Compensation Circuit. [Citation Graph (, )][DBLP]
    
    
23. 
    High Speed Ultra Low Voltage CMOS inverter. [Citation Graph (, )][DBLP]
    
    
24. 
    A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. [Citation Graph (, )][DBLP]
    
    
25. 
    Process Algebra Based SoC Test Scheduling for Test Time Minimization. [Citation Graph (, )][DBLP]
    
    
26. 
    Improving the Test of NoC-Based SoCs with Help of Compression Schemes. [Citation Graph (, )][DBLP]
    
    
27. 
    A Novel System on Chip (SoC) Test Solution. [Citation Graph (, )][DBLP]
    
    
28. 
    Testing Skew and Logic Faults in SoC Interconnects. [Citation Graph (, )][DBLP]
    
    
29. 
    A Programmable Frequency Divider in 0.18µm CMOS Library. [Citation Graph (, )][DBLP]
    
    
30. 
    Energy Recovery from High-Frequency Clocks Using DC-DC Converters. [Citation Graph (, )][DBLP]
    
    
31. 
    Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL. [Citation Graph (, )][DBLP]
    
    
32. 
    Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. [Citation Graph (, )][DBLP]
    
    
33. 
    Impact of Technology Scaling on Digital Subthreshold Circuits. [Citation Graph (, )][DBLP]
    
    
34. 
    Low Standby Power and Robust FinFET Based SRAM Design. [Citation Graph (, )][DBLP]
    
    
35. 
    CMOS Control Enabled Single-Type FET NASIC. [Citation Graph (, )][DBLP]
    
    
36. 
    A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. [Citation Graph (, )][DBLP]
    
    
37. 
    Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection. [Citation Graph (, )][DBLP]
    
    
38. 
    Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications. [Citation Graph (, )][DBLP]
    
    
39. 
    Performance Improvement of Physical Retiming with Shortcut Insertion. [Citation Graph (, )][DBLP]
    
    
40. 
    A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. [Citation Graph (, )][DBLP]
    
    
41. 
    A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. [Citation Graph (, )][DBLP]
    
    
42. 
    An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. [Citation Graph (, )][DBLP]
    
    
43. 
    A Real Case of Significant Scan Test Cost Reduction. [Citation Graph (, )][DBLP]
    
    
44. 
    A Network Based Functional Verification Method of IEEE 1394a PHY Core. [Citation Graph (, )][DBLP]
    
    
45. 
    Cohesive Coverage Management for Simulation and Formal Property Verification. [Citation Graph (, )][DBLP]
    
    
46. 
    Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. [Citation Graph (, )][DBLP]
    
    
47. 
    Memory Power Modeling - A Novel Approach. [Citation Graph (, )][DBLP]
    
    
48. 
    Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. [Citation Graph (, )][DBLP]
    
    
49. 
    Efficient High-Level Power Estimation for Multi-standard Wireless Systems. [Citation Graph (, )][DBLP]
    
    
50. 
    Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits. [Citation Graph (, )][DBLP]
    
    
51. 
    Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]
    
    
52. 
    SeReCon: A Secure Dynamic Partial Reconfiguration Controller. [Citation Graph (, )][DBLP]
    
    
53. 
    GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. [Citation Graph (, )][DBLP]
    
    
54. 
    Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. [Citation Graph (, )][DBLP]
    
    
55. 
    Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. [Citation Graph (, )][DBLP]
    
    
56. 
    Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. [Citation Graph (, )][DBLP]
    
    
57. 
    Characterisation of FPGA Clock Variability. [Citation Graph (, )][DBLP]
    
    
58. 
    A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. [Citation Graph (, )][DBLP]
    
    
59. 
    Flow Maximization for NoC Routing Algorithms. [Citation Graph (, )][DBLP]
    
    
60. 
    Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip. [Citation Graph (, )][DBLP]
    
    
61. 
    Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. [Citation Graph (, )][DBLP]
    
    
62. 
    Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier. [Citation Graph (, )][DBLP]
    
    
63. 
    A Versatile Linear Insertion Sorter Based on a FIFO Scheme. [Citation Graph (, )][DBLP]
    
    
64. 
    Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. [Citation Graph (, )][DBLP]
    
    
65. 
    Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. [Citation Graph (, )][DBLP]
    
    
66. 
    Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory. [Citation Graph (, )][DBLP]
    
    
67. 
    Standard Cell Like Via-Configurable Logic Block for Structured ASICs. [Citation Graph (, )][DBLP]
    
    
68. 
    SDVM-R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip. [Citation Graph (, )][DBLP]
    
    
69. 
    Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme. [Citation Graph (, )][DBLP]
    
    
70. 
    FPGA-Based Circuit Model Emulation of Quantum Algorithms. [Citation Graph (, )][DBLP]
    
    
71. 
    Petri Net Based Rapid Prototyping of Digital Complex System. [Citation Graph (, )][DBLP]
    
    
72. 
    Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. [Citation Graph (, )][DBLP]
    
    
73. 
    A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis. [Citation Graph (, )][DBLP]
    
    
74. 
    Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis. [Citation Graph (, )][DBLP]
    
    
75. 
    Efficient Realization of Strongly Indicating Function Blocks. [Citation Graph (, )][DBLP]
    
    
76. 
    Virtual Point-to-Point Links in Packet-Switched NoCs. [Citation Graph (, )][DBLP]
    
    
77. 
    Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. [Citation Graph (, )][DBLP]
    
    
78. 
    A Web Server Based Edge Detector Implementation in FPGA. [Citation Graph (, )][DBLP]
    
    
79. 
    Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. [Citation Graph (, )][DBLP]
    
    
80. 
    In Situ Design of Register Operations. [Citation Graph (, )][DBLP]
    
    
81. 
    An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design. [Citation Graph (, )][DBLP]
    
    
82. 
    Raising the Level of Abstraction for the Timing Verification of System-on-Chips. [Citation Graph (, )][DBLP]
    
    
83. 
    Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. [Citation Graph (, )][DBLP]
    
    
84. 
    Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. [Citation Graph (, )][DBLP]
    
    
85. 
    Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. [Citation Graph (, )][DBLP]
    
    
86. 
    NoC Power Estimation at the RTL Abstraction Level. [Citation Graph (, )][DBLP]
    
    
87. 
    Design of Fractal Image Compression on SOC. [Citation Graph (, )][DBLP]
    
    
88. 
    A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier. [Citation Graph (, )][DBLP]
    
    
89. 
    A Neural Stimulator Output Stage for Dodecapolar Electrodes. [Citation Graph (, )][DBLP]
    
    
90. 
    Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. [Citation Graph (, )][DBLP]
    
    
91. 
    Finding the Best Compromise in Compiling Compound Loops to Verilog. [Citation Graph (, )][DBLP]
    
    
92. 
    An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip. [Citation Graph (, )][DBLP]
    
    
93. 
    An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. [Citation Graph (, )][DBLP]
    
    
94. 
    Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading. [Citation Graph (, )][DBLP]
    
    
95. 
    A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. [Citation Graph (, )][DBLP]