Conferences in DBLP
Randal E. Bryant Multipliers and Dividers: Insights on Arithmetic Circuits Verification (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Bern , Christoph Meinel , Anna Slobodová Global rebuilding of OBDDs Avoiding Memory Requirement Maxima. [Citation Graph (0, 0)][DBLP ] Conf ] Ashvin Dsouza , Bard Bloom Generating BDD Models for Process Algebra Terms. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Basin , Nils Klarlund Hardware Verification using Monadic Second-Order Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Bengt Jonsson , Lars Kempe Verifying Safety Properties of a Class of Infinite-State Distributed Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Dingel , Thomas Filkorn Model Checking for Infinite State Systems Using Data Abstraction, Assumption-Commitment Style reasoning and Theorem Proving. [Citation Graph (0, 0)][DBLP ] Conf ] E. Pascal Gribomont , Didier Rossetto CAVEAT: Technique and Tool for Computer Aided VErification And Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] S. Rajan , Natarajan Shankar , Mandayam K. Srivas An Integration of Model Checking with Automated Proof Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Hojati , Robert K. Brayton Automatic Datapath Abstraction In Hardware Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Rauzy Toupie = µ-Calculus + Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Lalita Jategaonkar Jagadeesan , Carlos Puchol , James Von Olnhausen Safety Property Verification of ESTEREL Programs and Applications to Telecommunications Software. [Citation Graph (0, 0)][DBLP ] Conf ] E. Allen Emerson Methods for Mu-calculus Model Checking: A Tutorial (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Reif Andersen , Bart Vergauwen Efficient Checking of Behavioural Relations and Modal Assertions using Fixed-Point Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan Aziz , Vigyan Singhal , Felice Balarin It Usually Works: The Temporal Logic of Stochastic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Alur , Thomas A. Henzinger Local Liveness for Compositional Modeling of Fair Reactive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. McMillan Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Bouajjani , Yassine Lakhnech , Riadh Robbana From Duration Calculus To Linear Hybrid Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Oleg Sokolsky , Scott A. Smolka Local Model Checking for Real-Time Systems (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Thomas A. Henzinger , Pei-Hsin Ho Algorithmic Analysis of Nonlinear Hybrid Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Helmut Lescow On Polynomial-Size Programs Winning Finite-State Games. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram C. Krishnan , Anuj Puri , Robert K. Brayton , Pravin Varaiya The Rabin Index and Chain Automata, with Applications to Automatas and Games. [Citation Graph (0, 0)][DBLP ] Conf ] Moshe Y. Vardi An Automata-Theoretic Approach to Fair Realizability and Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan Aziz , Felice Balarin , Robert K. Brayton , M. D. DiBenedetto , Alexander Saldanha Supervisory Control of Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Cousot , Radhia Cousot Compositional and Inductive Semantic Definitions in Fixpoint, Equational, Constraint, Closure-condition, Rule-based and Game-Theoretic Form. [Citation Graph (0, 0)][DBLP ] Conf ] E. Allen Emerson , A. Prasad Sistla Utilizing Symmetry when Model Checking under Fairness Assumptions: An Automata-theoretic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Orna Kupferman Augmenting Branching Temporal Logics with Existential Quantification over Atomic Propositions. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Kurshan , Michael Merritt , Ariel Orda , Sonia R. Sachs Modelling Asynchrony with a Synchronous Model. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Esparza , Astrid Kiehn On the Model Checking Problem for Branching Time Logics and Basic Parallel Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Ásgeir Th. Eiríksson , Kenneth L. McMillan Using Formal Verification/Analysis Methods on the Critical Path in System Design: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Hsin Ho , Howard Wong-Toi Automated Analysis of an Audio Control Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Colin J. Fidge , Peter Kearney , Mark Utting Interactively Verifying a Simple Real-time Scheduler. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Dill , Howard Wong-Toi Verification of Real-Time Systems by Successive Over and Under Approximation. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Hulgaard , Steven M. Burns Efficient Timing Analysis of a Class of Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Bouajjani , Riadh Robbana Verifying omega-Regular Properties for a Subclass of Linear Hybrid Systems. [Citation Graph (0, 0)][DBLP ] Conf ] 