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Conferences in DBLP

Computer Aided Verification (CAV) (cav)
1990 (conf/cav/1990)

  1. Edmund M. Clarke
    Temporal Logic Model Checking: Two Techniques for Avoiding the State Explosion Problem. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:1- [Conf]
  2. Hans Eveking
    Automatic Verification of Extensions of Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:2-12 [Conf]
  3. Gérard Berthelot, Colette Johnen, Laure Petrucci
    PAPETRI: Environment for the Analysis of Petri Nets. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:13-22 [Conf]
  4. Olivier Coudert, Jean Christophe Madre, Christian Berthet
    Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:23-32 [Conf]
  5. Randal E. Bryant, Carl-Johan H. Seger
    Formal Verification of Digital Circuits Using Symbolic Ternary System Models. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:33-43 [Conf]
  6. Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi
    Vectorized Model Checking for Computation Tree Logic. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:44-53 [Conf]
  7. Carl Pixley
    Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:54-64 [Conf]
  8. Valérie Roy, Robert de Simone
    Auto/Autograph. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:65-75 [Conf]
  9. Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
    A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:76-85 [Conf]
  10. Paolo Camurati, M. Gilli, Paolo Prinetto, Matteo Sonza Reorda
    The Use of Model Checking in ATPG for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:86-95 [Conf]
  11. Jean Christophe Lloret, Pierre Azéma, François Vernadat
    Compositional Design and Verification of Communication Protocols, Using Labelled Petri Nets. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:96-105 [Conf]
  12. Linda A. Ness
    Issues Arising in the Analysis of L.0. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:106-115 [Conf]
  13. Michel Langevin
    Automated RTL Verification Based on Predicate Calculus. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:116-125 [Conf]
  14. Richard Lai, Ken R. Parker, Tharam S. Dillon
    On Using Protean To Verify ISO FTAM Protocol. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:126-135 [Conf]
  15. E. Allen Emerson, Aloysius K. Mok, A. Prasad Sistla, Jai Srinivasan
    Quantitative Temporal Reasoning. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:136-145 [Conf]
  16. David K. Probst, Hon F. Li
    Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:146-155 [Conf]
  17. Antti Valmari
    A Stubborn Attack On State Explosion. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:156-165 [Conf]
  18. Ryszard Janicki, Maciej Koutny
    Using Optimal Simulations to Reduce Reachability Graphs. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:166-175 [Conf]
  19. Patrice Godefroid
    Using Partial Orders to Improve Automatic Verification Methods. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:176-185 [Conf]
  20. Susanne Graf, Bernhard Steffen
    Compositional Minimization of Finite State Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:186-196 [Conf]
  21. Ahmed Bouajjani, Jean-Claude Fernandez, Nicolas Halbwachs
    Minimal Model Generation. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:197-203 [Conf]
  22. Bernhard Josko
    A Context Dependent Equivalence Relation Between Kripke Structures. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:204-213 [Conf]
  23. Gil Shurek, Orna Grumberg
    The Modular Framework of Computer-Aided Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:214-223 [Conf]
  24. Jerry R. Burch
    Verifying Liveness Properties by Verifying Safety Properties. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:224-232 [Conf]
  25. Costas Courcoubetis, Moshe Y. Vardi, Pierre Wolper, Mihalis Yannakakis
    Memory Efficient Algorithms for the Verification of Temporal Properties. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:233-242 [Conf]
  26. Wuxu Peng, S. Purushothaman
    A Unified Approach to the Deadlock Detection Problem in Networks of Communicating Finite State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:243-252 [Conf]
  27. Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
    Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:253-262 [Conf]
  28. Victor Yodaiken
    The Algebraic Feedback Product of Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:263-271 [Conf]
  29. Howard Wong-Toi, David L. Dill
    Synthesizing Processes and Schedulers from Temporal Specifications. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:272-281 [Conf]
  30. Christian H. Golaszewski, Robert P. Kurshan
    Task-Driven Supervisory Control of Discrete Event Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:282-291 [Conf]
  31. Ugo A. Buy, Robert Moll
    A Proof Lattice-Based Technique for Analyzing Liveness of Resource Controllers. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:292-301 [Conf]
  32. Paul Loewenstein, David L. Dill
    Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:302-311 [Conf]
  33. David A. Carrington, K. A. Robinson
    Computer Assistance for Program Refinement. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:312-321 [Conf]
  34. James M. Morris, Mark Howard
    Program Verification by Symbolic Execution of Hyperfinite Ideal Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:322-332 [Conf]
  35. Michel Barbeau, Gregor von Bochmann
    Extension of the Karp and Miller Procedure to Lotos Specifications. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:333-342 [Conf]
  36. Mark B. Josephs, Jan Tijmen Udding
    An Algebra for Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:343-352 [Conf]
  37. Eric Madelaine, Didier Vergamini
    Finiteness Conditions and Structural Construction of Automata for All Process Algebras. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:353-363 [Conf]
  38. Rance Cleaveland
    On Automatically Explaining Bisimulation Inequivalence. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:364-372 [Conf]
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