Conferences in DBLP
Colin Sterling Taming Infinite State Spaces. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Hüttel Silence is Golden: Branching Bisimilarity is Decidable for Context-Free Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Henri Korver Computing Distinguishing Formulas for Branching Bisimulation. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Reif Andersen , Glynn Winskel Compositional Checking of Satisfaction. [Citation Graph (0, 0)][DBLP ] Conf ] Rocco De Nicola , Alessandro Fantechi , Stefania Gnesi , Gioia Ristori An Action Based Framework for Verifying Logical and Behavioural Properties of Concurrent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rance Cleaveland , Bernhard Steffen A Linear-Time Model-Checking Algorithm for the Alternation-Free Modal Mu-Calculus. [Citation Graph (0, 0)][DBLP ] Conf ] A. Prasad Sistla , Lenore D. Zuck Automatic Temporal Verification of Buffer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Bevier , Jørgen F. Søgaard-Andersen Mechanically Checked Proofs of Kernel Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Stein Gjessing , Stein Krogdahl , Ellen Munthe-Kaas A Top Down Approach to the Formal Specification of SCI Cache Coherence. [Citation Graph (0, 0)][DBLP ] Conf ] George S. Avrunin , Ugo A. Buy , James C. Corbett Integer Programming in the Analysis of Concurrent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Barbeau , Gregor von Bochmann The Lotos Model of a Fault Protected System and its Verification Using a Petri Net Based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Anne Rasse Error Diagnosis in Finite Communicating Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ranga Vemuri , Anuradha Sridhar Temporal Precondition Verification of Design Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Huimin Lin PAM: A Process Algebra Manipulator. [Citation Graph (0, 0)][DBLP ] Conf ] Claus Torp Jensen The Concurrency Workbench with Priorities. [Citation Graph (0, 0)][DBLP ] Conf ] Sjouke Mauw , Gert J. Veltink A Proof Assistant for PSF. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Finkel , Laure Petrucci Avoiding State Exposion by Composition of Minimal Covering Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Claude Fernandez , Laurent Mounier "On the Fly" Verification of Behavioural Equivalences and Preorders. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Jard , Thierry Jéron Bounded-memory Algorithms for Verification On-the-fly. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Enders , Thomas Filkorn , Dirk Taubner Generating BDDs for Symbolic Model Checking in CCS. [Citation Graph (0, 0)][DBLP ] Conf ] Hiromi Hiraishi , Kiyoharu Hamaguchi , Hiroyuki Ochi , Shuzo Yajima Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Filkorn Functional Extension of Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Wenbo Mao , George J. Milne An Automated Proof Technique for Finite-State Machine Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Ed Brinksma From Data Structure to Process Structure. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Dill , Alan J. Hu , Howard Wong-Toi Checking for Language Inclusion Using Simulation Preorders. [Citation Graph (0, 0)][DBLP ] Conf ] Nicoletta De Francesco , Paola Inverardi A Semantic Driven Method to Check the Finiteness of CCS Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Mutz Using the HOL Prove Assistant for proving the Correctness of term Rewriting Rules reducing Terms of Sequential Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Nesi Mechanizing a Proof by Induction of Process Algebrs Specifications in Higher Order Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Carl-Johan H. Seger , Jeffrey J. Joyce A Two-Level Formal Verification Methodology using HOL and COSMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Linda Christoff , Ivan Christoff Efficient Algorithms for Verification of Equivalences for Probabilistic Processes. [Citation Graph (0, 0)][DBLP ] Conf ] David K. Probst , Hon F. Li Partial-Order Model Checking: A Guide for the Perplexed. [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Godefroid , Pierre Wolper Using Partial Orders for the Efficient Verification of Deadlock Freedom and Safety Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Feigenbaum , Jeremy A. Kahn , Carsten Lund Complexity Results for POMSET Languages. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Goldschlag Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider , Ramayya Kumar , Thomas Kropf Automating Most Parts of Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Nicollin , Joseph Sifakis An Overview and Synthesis on Timed Process Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Costas Courcoubetis Minimum and Maximum Delay Problems in Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoharu Hamaguchi , Hiromi Hiraishi , Shuzo Yajima Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Armen Gabrielian , R. Iyer Verifying Properties of HMS Machine Specifications of Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Jeffrey A Linear Time Process Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Uno Holmer , Kim Guldstrand Larsen , Wang Yi Deciding Properties of Regular Real Time Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Costas Courcoubetis , Susanne Graf , Joseph Sifakis An Algebra of Boolean Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Langevin , Eduard Cerny Comparing Generic State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Gjalt G. de Jong An Automata Theoretic Approach to Temporal Logic. [Citation Graph (0, 0)][DBLP ] Conf ] 