Conferences in DBLP
F. Erich Marschner Practical Challenges for Industrial Formal Verification Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Roger B. Hughes Formal Verification of Digital Systems, from ASICs to HW/SW Codesign - a Pragmatic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Arne Borälv The Industrial Success of Verification Tools Based on Stålmarck's Method. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Rowe Formal Verification - Applications & Case Studies. [Citation Graph (0, 0)][DBLP ] Conf ] Abelardo Pardo , Gary D. Hachtel Automatic Abstraction Techniques for Propositional µ-calculus Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. McMillan A Compositional Rule for Hardware Design Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Orna Kupferman , Moshe Y. Vardi Model Checking Revisited. [Citation Graph (0, 0)][DBLP ] Conf ] Roope Kaivola Using Compositional Preorders in the Verification of Sliding Window Protocal. [Citation Graph (0, 0)][DBLP ] Conf ] David Cyrluk , M. Oliver Möller , Harald Rueß An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Susanne Graf , Hassen Saïdi Construction of Abstract State Graphs with PVS. [Citation Graph (0, 0)][DBLP ] Conf ] Adam L. Turk , Scott T. Probst , Gary J. Powers Verification of a Chemical Process Leak Test Procedure. [Citation Graph (0, 0)][DBLP ] Conf ] Gila Kamhi , Osnat Weissberg , Limor Fix Automatic Datapath Extraction for Efficient Usage of HDD. [Citation Graph (0, 0)][DBLP ] Conf ] Nils Klarlund An n log n Algorithm for Online BDD Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Christel Baier , Holger Hermanns Weak Bisimulation for Fully Probabilistic Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Dominique Bolignano Towards a Mechanization of Cryptographic Protocal Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Y. S. Ramakrishna , C. R. Ramakrishnan , I. V. Ramakrishnan , Scott A. Smolka , Terrance Swift , David Scott Warren Efficient Model Checking Using Tabled Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Kathi Fisler Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard Boigelot , Louis Bronne , Stéphane Rassart An Improved Reachability Analysis Method for Strongly Linear Hybrid Systems (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Marius Bozga , Oded Maler , Amir Pnueli , Sergio Yovine Some Progress in the Symbolic Verification of Timed Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Serdar Tasiran , Robert K. Brayton STARI: A Case Study in Compositional and Hierarchical Timing Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Cimatti , Fausto Giunchiglia , Paolo Pecchiari , Bruno Pietra , Joe Profeta , Dario Romano , Paolo Traverso , Bing Yu A Provably Correct Embedded Verifier for the Certification of Safety Critical Software. [Citation Graph (0, 0)][DBLP ] Conf ] Geoff Barrett , Anthony McIsaac Model Checking in a Microprocessor Design Project. [Citation Graph (0, 0)][DBLP ] Conf ] David Harel Some Thoughts on Statecharts, 13 Years Later. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor Gyuris , A. Prasad Sistla On-the-Fly Model Checking Under Fairness That Exploits Symmetry. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Pandey , Randal E. Bryant Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Stern , David L. Dill Parallelizing the Murphi Verifier. [Citation Graph (0, 0)][DBLP ] Conf ] Ilan Beer , Shoham Ben-David , Cindy Eisner , Yoav Rodeh Efficient Detection of Vacuity in ACTL Formulaas. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Immerman , Moshe Y. Vardi Model Checking and Transitive-Closure Logic. [Citation Graph (1, 0)][DBLP ] Conf ] Gérard Berry Boolean and 2-adic Numbers Based Techniques for Verifying Synchronous Design. [Citation Graph (0, 0)][DBLP ] Conf ] Gérard Cécé , Alain Finkel Programs with Quasi-Stable Channels are Effectively Recognizable (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] William Chan , Richard J. Anderson , Paul Beame , David Notkin Combining Constraint Solving and Symbolic Model Checking for a Class of a Systems with Non-linear Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ilkka Kokkarinen , Doron Peled , Antti Valmari Relaxed Visibility Enhances Partial Order Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Alur , Robert K. Brayton , Thomas A. Henzinger , Shaz Qadeer , Sriram K. Rajamani Partial-Order Reduction in Symbolic State Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Melzer , Stefan Römer Deadlock Checking Using Net Unfoldings. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Sawada , Warren A. Hunt Jr. Trace Table Based Approach for Pipeline Microprocessor Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yuan , Jian Shen , Jacob A. Abraham , Adnan Aziz On Combining Formal and Informal Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev , Randal E. Bryant , Alok Jain Efficient Modeling of Memory Arrays in Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Tevfik Bultan , Richard Gerber , William Pugh Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] A. Prasad Sistla Parametrized Verification of Linear Networks Using Automata as Invariants. [Citation Graph (0, 0)][DBLP ] Conf ] Yonit Kesten , Oded Maler , Monica Marcus , Amir Pnueli , Elad Shahar Symbolic Model Checking with Rich ssertional Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Hassen Saïdi The Invariant Checker: Automated Deductive Verification of Reactive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Grahlmann The PEP Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Naomi Lindenstrauss , Yehoshua Sagiv , Alexander Serebrenik TermiLog: A System for Checking Termination of Queries to Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Kelb , Tiziana Margaria , Michael Mendler , Claudia Gsottberger MOSEL: A Sound and Efficient Tool for M2L(Str). [Citation Graph (0, 0)][DBLP ] Conf ] Sérgio Vale Aguiar Campos , Edmund M. Clarke , Marius Minea The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kim Guldstrand Larsen , Paul Pettersson , Wang Yi UPPAAL: Status & Developments. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas A. Henzinger , Pei-Hsin Ho , Howard Wong-Toi HYTECH: A Model Checker for Hybrid Systems. [Citation Graph (0, 0)][DBLP ] Conf ] A. Prasad Sistla , L. Miliades , Viktor Gyuris SMC: A Symmetry Based Model Checker for Verification of Liveness Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Biere µcke - Efficient µ-Calculus Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Kimmo Varpaaniemi , Keijo Heljanko , Johan Lilius prod 3.2: An Advanced Tool for Efficient Reachability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Godefroid VeriSoft: A Tool for the Automatic Analysis of Concurrent Reactive Software. [Citation Graph (0, 0)][DBLP ] Conf ] Ilan Beer , Shoham Ben-David , Cindy Eisner , Daniel Geist , Leonid Gluhovsky , Tamir Heyman , Avner Landver , P. Paanah , Yoav Rodeh , G. Ronin , Yaron Wolfsthal RuleBase: Model Checking at IBM. [Citation Graph (0, 0)][DBLP ] Conf ] 