Conferences in DBLP
Robert K. Brayton Logic Synthesis and Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Hu , David L. Dill Efficient Verification with BDDs using Implicitly Conjoined Invariants. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Allan L. Fisher Parametric Circuit Representation Using Inductive Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Felice Balarin , Alberto L. Sangiovanni-Vincentelli An Iterative Approach to Language Containment. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Hojati , Robert K. Brayton , Robert P. Kurshan BDD-Based Debugging Of Design Using Language Containment and Fair CTL. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Wolper , Denis Leroy Reliable Hashing without Collosion Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Susanne Graf , Claire Loiseaux A Tool for Symbolic Program Verification and Abstration. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Claude Fernandez , Alain Kerbrat , Laurent Mounier Symbolic Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Yonit Kesten , Zohar Manna , Hugh McGuire , Amir Pnueli A Decision Algorithm for Full Propositional Temporal Logic. [Citation Graph (0, 0)][DBLP ] Conf ] A. S. Krishnakumar Reachability and Recurrence in Extended Finite State Machines: Modular Vector Addition Systems. [Citation Graph (0, 0)][DBLP ] Conf ] June-Kyung Rho , Fabio Somenzi Automatic Generation of Network Invariants for the Verification of Iterative Sequential Systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. Kutty , Y. S. Ramakrishna , Louise E. Moser , Laura K. Dillon , P. M. Melliar-Smith A Graphical Interval Logic Toolset for Verifying Concurrent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hardi Hungar Combining Model Checking and Theorem Proving to Verify Parallel Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Kurshan , Leslie Lamport Verification of a Multiplier: 64 Bits and Beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Pravin Varaiya Protocol Design for an Automated Highway System (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Alur , Costas Courcoubetis , Thomas A. Henzinger Computing Accumulated Delays in Real-time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Oded Maler , Amir Pnueli Reachability Analysis of Planar Multi-limear Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mihalis Yannakakis , David Lee An Efficient Algorithm for Minimizing Real-time Transition Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Costas Courcoubetis , Werner Damm , Bernhard Josko Verification of timing Properties of VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] William K. C. Lam , Robert K. Brayton Alternating RQ Timed Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Karlis Cerans , Jens Chr. Godskesen , Kim Guldstrand Larsen Timed Modal Specification - Theory and Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Wilding A Mechanically Verified Application for a Mechanically Verified Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Natarajan Shankar Verification of Real-Time Systems Using PVS. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lincoln , John M. Rushby The Formal Verification of an Algorithm for Interactive Consistency under a Hybrid Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Jørgen F. Søgaard-Andersen , Stephen J. Garland , John V. Guttag , Nancy A. Lynch , Anna Pogosyants Computer-Assisted Simulation Proofs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. C. Gordon A Verifier and Timing Analyser for Simple Imperative Programs (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Tomohiro Yoneda , Atsufumi Shibayama , Bernd-Holger Schlingloff , Edmund M. Clarke Efficient Verification of Parallel Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Halbwachs Delay Analysis in Synchronous Programs. [Citation Graph (0, 0)][DBLP ] Conf ] M. Jourdan , Florence Maraninchi , Alfredo Olivero Verifying Quantitative Real-Time Properties of Synchronous Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Hennessy , Xinxin Liu A Modal Logic for Message passing Processes (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Ed Brinksma , Rom Langerak , Peter Broekroelofs Functionality Decomposition by Compositional Correstness Preserving Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] E. Allen Emerson , Charanjit S. Jutla , A. Prasad Sistla On Model-Checking for Fragments of µ-Calculus. [Citation Graph (0, 0)][DBLP ] Conf ] Antti Valmari On-the-Fly Verification with Stubborn Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Doron Peled All from One, One for All: on Model Checking Using Representatives. [Citation Graph (0, 0)][DBLP ] Conf ] David K. Probst , Hon F. Li Verifying Timed Behavior Automata with Input/Output Critical Races. [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Godefroid , Didier Pirottin Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Thomas Filkorn , Somesh Jha Exploiting Symmetry In Temporal Logic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] E. Allen Emerson , A. Prasad Sistla Symmetry and Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Dams , Orna Grumberg , Rob Gerth Generation of Reduced Models for Checking Fragments of CTL. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Kurshan , Michael Merritt , Ariel Orda , Sonia R. Sachs A Structural Linearization Principle for Processes. [Citation Graph (0, 0)][DBLP ] Conf ] 