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Conferences in DBLP
Modulo scheduling without overlapped lifetimes. [Citation Graph (, )][DBLP]
Synchronous objects with scheduling policies: introducing safe shared memory in lustre. [Citation Graph (, )][DBLP]
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP]
PTIDES on flexible task graph: real-time embedded systembuilding from theory to practice. [Citation Graph (, )][DBLP]
A compiler optimization to reduce soft errors in register files. [Citation Graph (, )][DBLP]
Raced profiles: efficient selection of competing compiler optimizations. [Citation Graph (, )][DBLP]
Eliminating the call stack to save RAM. [Citation Graph (, )][DBLP]
Live-range unsplitting for faster optimal coalescing. [Citation Graph (, )][DBLP]
Push-assisted migration of real-time tasks in multi-core processors. [Citation Graph (, )][DBLP]
Software transactional memory for multicore embedded systems. [Citation Graph (, )][DBLP]
Synergistic execution of stream programs on multicores with accelerators. [Citation Graph (, )][DBLP]
Towards device emulation code generation. [Citation Graph (, )][DBLP]
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). [Citation Graph (, )][DBLP]
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring. [Citation Graph (, )][DBLP]
Tracing interrupts in embedded software. [Citation Graph (, )][DBLP]
Addressing the challenges of DBT for the ARM architecture. [Citation Graph (, )][DBLP]
Integrating hardware and software information flow analyses. [Citation Graph (, )][DBLP]
Specification and verification of time requirements with CCSL and Esterel. [Citation Graph (, )][DBLP]
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