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Conferences in DBLP

Languages, Compilers, and Tools for Embedded Systems (LCTES) (lctrts)
2010 (conf/lctrts/2010)

  1. Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. [Citation Graph (, )][DBLP]

  2. Versatile system-level memory-aware platform description approach for embedded MPSoCs. [Citation Graph (, )][DBLP]

  3. Operation and data mapping for CGRAs with multi-bank memory. [Citation Graph (, )][DBLP]

  4. Look into details: the benefits of fine-grain streaming buffer analysis. [Citation Graph (, )][DBLP]

  5. Modeling structured event streams in system level performance analysis. [Citation Graph (, )][DBLP]

  6. Translating concurrent action oriented specifications to synchronous guarded actions. [Citation Graph (, )][DBLP]

  7. Contracts for modular discrete controller synthesis. [Citation Graph (, )][DBLP]

  8. Semi-automatic derivation of timing models for WCET analysis. [Citation Graph (, )][DBLP]

  9. Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. [Citation Graph (, )][DBLP]

  10. Compiler directed network-on-chip reliability enhancement for chip multiprocessors. [Citation Graph (, )][DBLP]

  11. Improving both the performance benefits and speed of optimization phase sequence searches. [Citation Graph (, )][DBLP]

  12. An efficient code update scheme for DSP applications in mobile embedded systems. [Citation Graph (, )][DBLP]

  13. Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing. [Citation Graph (, )][DBLP]

  14. Integrating safety analysis into the model-based development toolchain of automotive embedded systems. [Citation Graph (, )][DBLP]

  15. Sampling-based program execution monitoring. [Citation Graph (, )][DBLP]

  16. Cache vulnerability equations for protecting data in embedded processor caches from soft errors. [Citation Graph (, )][DBLP]

  17. Resilience analysis: tightening the CRPD bound for set-associative caches. [Citation Graph (, )][DBLP]

  18. RNFTL: a reuse-aware NAND flash translation layer for flash memory. [Citation Graph (, )][DBLP]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002