|
|
Conferences in DBLP
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. [Citation Graph (, )][DBLP]
Versatile system-level memory-aware platform description approach for embedded MPSoCs. [Citation Graph (, )][DBLP]
Operation and data mapping for CGRAs with multi-bank memory. [Citation Graph (, )][DBLP]
Look into details: the benefits of fine-grain streaming buffer analysis. [Citation Graph (, )][DBLP]
Modeling structured event streams in system level performance analysis. [Citation Graph (, )][DBLP]
Translating concurrent action oriented specifications to synchronous guarded actions. [Citation Graph (, )][DBLP]
Contracts for modular discrete controller synthesis. [Citation Graph (, )][DBLP]
Semi-automatic derivation of timing models for WCET analysis. [Citation Graph (, )][DBLP]
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. [Citation Graph (, )][DBLP]
Compiler directed network-on-chip reliability enhancement for chip multiprocessors. [Citation Graph (, )][DBLP]
Improving both the performance benefits and speed of optimization phase sequence searches. [Citation Graph (, )][DBLP]
An efficient code update scheme for DSP applications in mobile embedded systems. [Citation Graph (, )][DBLP]
Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing. [Citation Graph (, )][DBLP]
Integrating safety analysis into the model-based development toolchain of automotive embedded systems. [Citation Graph (, )][DBLP]
Sampling-based program execution monitoring. [Citation Graph (, )][DBLP]
Cache vulnerability equations for protecting data in embedded processor caches from soft errors. [Citation Graph (, )][DBLP]
Resilience analysis: tightening the CRPD bound for set-associative caches. [Citation Graph (, )][DBLP]
RNFTL: a reuse-aware NAND flash translation layer for flash memory. [Citation Graph (, )][DBLP]
|
