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Conferences in DBLP

Computer Aided Verification (CAV) (cav)
2001 (conf/cav/2001)

  1. David Lorge Parnas
    Software Documentation and the Verification Process. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:1- [Conf]
  2. Kedar S. Namjoshi
    Certifying Model Checkers. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:2-13 [Conf]
  3. Yves Bertot
    Formalizing a JVML Verifier for Initialization in a Theorem Prover. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:14-24 [Conf]
  4. Abhik Roychoudhury, I. V. Ramakrishnan
    Automated Inductive Verification of Parameterized Protocols. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:25-37 [Conf]
  5. Girish Bhat, Rance Cleaveland, Alex Groce
    Efficient Model Checking Via Büchi Tableau Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:38-52 [Conf]
  6. Paul Gastin, Denis Oddoux
    Fast LTL to Büchi Automata Translation. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:53-65 [Conf]
  7. Hana Chockler, Orna Kupferman, Robert P. Kurshan, Moshe Y. Vardi
    A Practical Approach to Coverage in Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:66-78 [Conf]
  8. Agostino Dovier, Carla Piazza, Alberto Policriti
    A Fast Bisimulation Algorithm. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:79-90 [Conf]
  9. A. Prasad Sistla, Patrice Godefroid
    Symmetry and Reduced Symmetry in Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:91-103 [Conf]
  10. Andreas Kuehlmann, Jason Baumgartner
    Transformation-Based Verification Using Generalized Retiming. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:104-117 [Conf]
  11. Gianpiero Cabodi
    Meta-BDDs: A Decomposed Representation for Layered Symbolic Manipulation of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:118-130 [Conf]
  12. John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
    CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:131-143 [Conf]
  13. Yoav Rodeh, Ofer Strichman
    Finite Instantiations in Equivalence Logic with Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:144-154 [Conf]
  14. Alexander Asteroth, Christel Baier, Ulrich Aßmann
    Model Checking with Formula-Dependent Abstract Models. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:155-168 [Conf]
  15. Rajeev Alur, Bow-Yaw Wang
    Verifying Network Protocol Implementations by Symbolic Refinement Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:169-181 [Conf]
  16. Hao Zheng, Eric Mercer, Chris J. Myers
    Automatic Abstraction for Verification of Timed Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:182-193 [Conf]
  17. Marta Z. Kwiatkowska, Gethin Norman, Roberto Segala
    Automated Verification of a Randomized Distributed Consensus Protocol Using Cadence SMV and PRISM. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:194-206 [Conf]
  18. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
    Analysis of Recursive State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:207-220 [Conf]
  19. Tamarah Arons, Amir Pnueli, Sitvanit Ruah, Jiazhao Xu, Lenore D. Zuck
    Parameterized Verification with Automatically Computed Inductive Assertions. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:221-234 [Conf]
  20. Miroslav N. Velev, Randal E. Bryant
    EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:235-240 [Conf]
  21. Dawn Xiaodong Song, Adrian Perrig, Doantam Phan
    AGVI - Automatic Generation, Verification, and Implementation of Security Protocols. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:241-245 [Conf]
  22. Jean-Christophe Filliâtre, Sam Owre, Harald Rueß, Natarajan Shankar
    ICS: Integrated Canonizer and Solver. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:246-249 [Conf]
  23. Stefan Blom, Wan Fokkink, Jan Friso Groote, Izak van Langevelde, Bert Lisser, Jaco van de Pol
    µCRL: A Toolset for Analysing Algebraic Specifications. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:250-254 [Conf]
  24. Martin Leucker, Thomas Noll
    Truth/SLC - A Parallel Verification Platform for Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:255-259 [Conf]
  25. Thomas Ball, Sriram K. Rajamani
    The SLAM Toolkit. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:260-264 [Conf]
  26. Xavier Leroy
    Java Bytecode Verification: An Overview. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:265-285 [Conf]
  27. Dennis Dams, Yassine Lakhnech, Martin Steffen
    Iterating Transducers. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:286-297 [Conf]
  28. Giorgio Delzanno, Jean-François Raskin, Laurent Van Begin
    Attacking Symbolic State Explosion. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:298-310 [Conf]
  29. Monika Maidl
    A Unifying Model Checking Approach for Safety Properties of Parameterized Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:311-323 [Conf]
  30. Javier Esparza, Stefan Schwoon
    A BDD-Based Model Checker for Recursive Programs. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:324-336 [Conf]
  31. Luca de Alfaro
    Model Checking the World Wide Web. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:337-349 [Conf]
  32. Orna Grumberg, Tamir Heyman, Assaf Schuster
    Distributed Symbolic Model Checking for µ-Calculus. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:350-362 [Conf]
  33. Ilan Beer, Shoham Ben-David, Cindy Eisner, Dana Fisman, Anna Gringauze, Yoav Rodeh
    The Temporal Logic Sugar. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:363-367 [Conf]
  34. Aurore Annichini, Ahmed Bouajjani, Mihaela Sighireanu
    TReX: A Tool for Reachability Analysis of Complex Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:368-372 [Conf]
  35. Peer Johannsen
    BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:373-377 [Conf]
  36. Vladimir Levin, Hüsnü Yenigün
    SDLcheck: A Model Checking Tool. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:377- [Conf]
  37. Vivek K. Shanbhag, K. Gopinath, Markku Turunen, Ari Ahtiainen, Matti Luukkainen
    EASN: Integrating ASN.1 and Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:382-386 [Conf]
  38. Nina Amla, E. Allen Emerson, Robert P. Kurshan, Kedar S. Namjoshi
    Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:387-390 [Conf]
  39. Etienne Closse, Michel Poize, Jacques Pulou, Joseph Sifakis, Patrick Venter, Daniel Weil, Sergio Yovine
    TAXYS: A Tool for the Development and Verification of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:391-395 [Conf]
  40. Ranjit Jhala, Kenneth L. McMillan
    Microarchitecture Verification by Compositional Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:396-410 [Conf]
  41. J. Strother Moore
    Rewriting for Symbolic Execution of State Machine Models. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:411-422 [Conf]
  42. Tamarah Arons
    Using Timestamping and History Variables to Verify Sequential Consistency. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:423-435 [Conf]
  43. Fady Copty, Limor Fix, Ranan Fraer, Enrico Giunchiglia, Gila Kamhi, Armando Tacchella, Moshe Y. Vardi
    Benefits of Bounded Model Checking at an Industrial Setting. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:436-453 [Conf]
  44. Per Bjesse, Tim Leonard, Abdel Mokkedem
    Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:454-464 [Conf]
  45. Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane
    Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m). [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:465-477 [Conf]
  46. Yasmina Abdeddaïm, Oded Maler
    Job-Shop Scheduling Using Timed Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:478-492 [Conf]
  47. Kim Guldstrand Larsen, Gerd Behrmann, Ed Brinksma, Ansgar Fehnker, Thomas Hune, Paul Pettersson, Judi Romijn
    As Cheap as Possible: Efficient Cost-Optimal Reachability for Priced Timed Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:493-505 [Conf]
  48. Zhe Dang
    Binary Reachability Analysis of Pushdown Timed Automata with Dense Clocks. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:506-518 [Conf]
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