Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
2007 (conf/micro/2007)

1. 
   Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. [Citation Graph (, )][DBLP]
   
   
2. 
   Process Variation Tolerant 3T1D-Based Cache Architectures. [Citation Graph (, )][DBLP]
   
   
3. 
   Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. [Citation Graph (, )][DBLP]
   
   
4. 
   Optimal versus Heuristic Global Code Scheduling. [Citation Graph (, )][DBLP]
   
   
5. 
   Global Multi-Threaded Instruction Scheduling. [Citation Graph (, )][DBLP]
   
   
6. 
   Revisiting the Sequential Programming Model for Multi-Core. [Citation Graph (, )][DBLP]
   
   
7. 
   Penelope: The NBTI-Aware Processor. [Citation Graph (, )][DBLP]
   
   
8. 
   Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. [Citation Graph (, )][DBLP]
   
   
9. 
   Self-calibrating Online Wearout Detection. [Citation Graph (, )][DBLP]
   
   
10. 
    Implementing Signatures for Transactional Memory. [Citation Graph (, )][DBLP]
    
    
11. 
    Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. [Citation Graph (, )][DBLP]
    
    
12. 
    Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
13. 
    Impact of Cache Coherence Protocols on the Processing of Network Traffic. [Citation Graph (, )][DBLP]
    
    
14. 
    Flattened Butterfly Topology for On-Chip Networks. [Citation Graph (, )][DBLP]
    
    
15. 
    Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. [Citation Graph (, )][DBLP]
    
    
16. 
    Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. [Citation Graph (, )][DBLP]
    
    
17. 
    Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. [Citation Graph (, )][DBLP]
    
    
18. 
    Leveraging 3D Technology for Improved Reliability. [Citation Graph (, )][DBLP]
    
    
19. 
    Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. [Citation Graph (, )][DBLP]
    
    
20. 
    FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. [Citation Graph (, )][DBLP]
    
    
21. 
    Microarchitectural Design Space Exploration Using an Architecture-Centric Approach. [Citation Graph (, )][DBLP]
    
    
22. 
    Informed Microarchitecture Design Space Exploration Using Workload Dynamics. [Citation Graph (, )][DBLP]
    
    
23. 
    Time Interpolation: So Many Metrics, So Few Registers. [Citation Graph (, )][DBLP]
    
    
24. 
    Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications. [Citation Graph (, )][DBLP]
    
    
25. 
    A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. [Citation Graph (, )][DBLP]
    
    
26. 
    Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. [Citation Graph (, )][DBLP]
    
    
27. 
    A Framework for Providing Quality of Service in Chip Multi-Processors. [Citation Graph (, )][DBLP]
    
    
28. 
    A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. [Citation Graph (, )][DBLP]
    
    
29. 
    Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. [Citation Graph (, )][DBLP]
    
    
30. 
    Composable Lightweight Processors. [Citation Graph (, )][DBLP]
    
    
31. 
    The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. [Citation Graph (, )][DBLP]
    
    
32. 
    Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. [Citation Graph (, )][DBLP]
    
    
33. 
    Scavenger: A New Last Level Cache Architecture with Global Block Priority. [Citation Graph (, )][DBLP]
    
    
34. 
    Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. [Citation Graph (, )][DBLP]
    
    
35. 
    Emulating Optimal Replacement with a Shepherd Cache. [Citation Graph (, )][DBLP]