Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
2009 (conf/micro/2009)

1. 
   POWER7 multi-core processor design. [Citation Graph (, )][DBLP]
   
   
2. 
   Characterizing and mitigating the impact of process variations on phase change based memory systems. [Citation Graph (, )][DBLP]
   
   
3. 
   Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. [Citation Graph (, )][DBLP]
   
   
4. 
   Characterizing flash memory: anomalies, observations, and applications. [Citation Graph (, )][DBLP]
   
   
5. 
   Complexity effective memory access scheduling for many-core accelerator architectures. [Citation Graph (, )][DBLP]
   
   
6. 
   Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. [Citation Graph (, )][DBLP]
   
   
7. 
   DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage. [Citation Graph (, )][DBLP]
   
   
8. 
   Tree register allocation. [Citation Graph (, )][DBLP]
   
   
9. 
   Portable compiler optimisation across embedded programs and microarchitectures using machine learning. [Citation Graph (, )][DBLP]
   
   
10. 
    Improving cache lifetime reliability at ultra-low voltages. [Citation Graph (, )][DBLP]
    
    
11. 
    ZerehCache: armoring cache architectures in high defect density technologies. [Citation Graph (, )][DBLP]
    
    
12. 
    Low Vccmin fault-tolerant cache with highly predictable performance. [Citation Graph (, )][DBLP]
    
    
13. 
    mSWAT: low-cost hardware fault detection and diagnosis for multicore systems. [Citation Graph (, )][DBLP]
    
    
14. 
    BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. [Citation Graph (, )][DBLP]
    
    
15. 
    EazyHTM: eager-lazy hardware transactional memory. [Citation Graph (, )][DBLP]
    
    
16. 
    Proactive transaction scheduling for contention management. [Citation Graph (, )][DBLP]
    
    
17. 
    Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures. [Citation Graph (, )][DBLP]
    
    
18. 
    A microarchitecture-based framework for pre- and post-silicon power delivery analysis. [Citation Graph (, )][DBLP]
    
    
19. 
    Reducing peak power with a table-driven adaptive processor core. [Citation Graph (, )][DBLP]
    
    
20. 
    Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. [Citation Graph (, )][DBLP]
    
    
21. 
    An hybrid eDRAM/SRAM macrocell to implement first-level data caches. [Citation Graph (, )][DBLP]
    
    
22. 
    Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. [Citation Graph (, )][DBLP]
    
    
23. 
    In-network coherence filtering: snoopy coherence without broadcasts. [Citation Graph (, )][DBLP]
    
    
24. 
    SCARAB: a single cycle adaptive routing and bufferless network. [Citation Graph (, )][DBLP]
    
    
25. 
    Low-cost router microarchitecture for on-chip networks. [Citation Graph (, )][DBLP]
    
    
26. 
    Why design must change: rethinking digital design. [Citation Graph (, )][DBLP]
    
    
27. 
    Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. [Citation Graph (, )][DBLP]
    
    
28. 
    Application-aware prioritization mechanisms for on-chip networks. [Citation Graph (, )][DBLP]
    
    
29. 
    A case for dynamic frequency tuning in on-chip networks. [Citation Graph (, )][DBLP]
    
    
30. 
    Light speed arbitration and flow control for nanophotonic interconnects. [Citation Graph (, )][DBLP]
    
    
31. 
    Coordinated control of multiple prefetchers in multi-core systems. [Citation Graph (, )][DBLP]
    
    
32. 
    Improving memory bank-level parallelism in the presence of prefetching. [Citation Graph (, )][DBLP]
    
    
33. 
    ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem. [Citation Graph (, )][DBLP]
    
    
34. 
    Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance. [Citation Graph (, )][DBLP]
    
    
35. 
    Using a configurable processor generator for computer architecture prototyping. [Citation Graph (, )][DBLP]
    
    
36. 
    Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. [Citation Graph (, )][DBLP]
    
    
37. 
    Ordering decoupled metadata accesses in multiprocessors. [Citation Graph (, )][DBLP]
    
    
38. 
    Control flow obfuscation with information flow tracking. [Citation Graph (, )][DBLP]
    
    
39. 
    Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. [Citation Graph (, )][DBLP]
    
    
40. 
    Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems. [Citation Graph (, )][DBLP]
    
    
41. 
    A tagless coherence directory. [Citation Graph (, )][DBLP]
    
    
42. 
    Tribeca: design for PVT variations with local recovery and fine-grained adaptation. [Citation Graph (, )][DBLP]
    
    
43. 
    The BubbleWrap many-core: popping cores for sequential acceleration. [Citation Graph (, )][DBLP]
    
    
44. 
    Multiple clock and voltage domains for chip multi processors. [Citation Graph (, )][DBLP]
    
    
45. 
    McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. [Citation Graph (, )][DBLP]
    
    
46. 
    Characterizing the resource-sharing levels in the UltraSPARC T2 processor. [Citation Graph (, )][DBLP]
    
    
47. 
    Execution leases: a hardware-supported mechanism for enforcing strong non-interference. [Citation Graph (, )][DBLP]
    
    
48. 
    Optimizing shared cache behavior of chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
49. 
    SHARP control: controlled shared cache management in chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
50. 
    Adaptive line placement with the set balancing cache. [Citation Graph (, )][DBLP]
    
    
51. 
    Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. [Citation Graph (, )][DBLP]
    
    
52. 
    Finding concurrency bugs with context-aware communication graphs. [Citation Graph (, )][DBLP]
    
    
53. 
    Offline symbolic analysis for multi-processor execution replay. [Citation Graph (, )][DBLP]
    
    
54. 
    Architecting a chunk-based memory race recorder in modern CMPs. [Citation Graph (, )][DBLP]