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Conferences in DBLP

Cooperation, Concurrence and Communication Project (ccc)
1991 (conf/ccc/1991)

  1. Patrice Quinton, Yves Robert
    Algorithms and Parallel VLSI Architectures. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:1-10 [Conf]
  2. John G. McWhirter, Ian K. Proudler
    Orthogonal lattice algorithms for adaptive filtering and beamforming. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:11-24 [Conf]
  3. Miguel Valero-García, Juan J. Navarro, José J. M. Liabería, Mateo Valero, Tomás Lang
    Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:25-38 [Conf]
  4. Marc Moonen
    Algorithms and architectures for recursive total least squares estimation. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:39-46 [Conf]
  5. Rami G. Melhem, John C. Ramirez
    Meshes with flexible redundancy. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:47-58 [Conf]
  6. Selim G. Akl, John M. Calvert, Ivan Stojmenovic
    Systolic generation of derangements. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:59-70 [Conf]
  7. Rumen Andonov, Frédéric Gruau
    A 2D toroidal systolic array for the knapsack problem. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:71-78 [Conf]
  8. Joost-Pieter Katoen, Berry Schoenmakers
    A Parallel program for the recognition of P-Invariant segments. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:79-84 [Conf]
  9. Gur Saran Adhar, Shietung Peng
    Parallel algorithms for finding connected, independent and total domination in interval graphs. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:85-90 [Conf]
  10. Frank K. H. A. Dehne, Andrew Rau-Chaplin
    Parallel algorithms for color image quantization on hypercubes and meshes. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:91-96 [Conf]
  11. Stéphane Ubéda
    A parallel thinning algorithm using the bounding boxes technique. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:97-102 [Conf]
  12. A. J. van der Veen, Patrick Dewilde
    Time-varying system theory for computational networks. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:103-130 [Conf]
  13. Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
    Generalized cycle shrinking. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:131-144 [Conf]
  14. Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis
    Direct mapping of nested loops on piecewise regular processor arrays. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:145-150 [Conf]
  15. Vincent Van Dongen
    From systolic to periodic array design. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:151-162 [Conf]
  16. Tanguy Risset
    Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:163-174 [Conf]
  17. Ravi Varadarajan, Bhavani Ravichandran
    Refinement based algorithm mapping techniques for linear systolic arrays. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:175-180 [Conf]
  18. Jingling Xue, Christian Lengauer
    Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:181-186 [Conf]
  19. Sanjay V. Rajopadhye
    An improved systolic algorithm for the algebraic path problem. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:187-198 [Conf]
  20. Philippe Clauss, Catherine Mongenet, Guy-René Perrin
    Synthesis of size-optimal toroidal arrays for the algebraic path problem. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:199-204 [Conf]
  21. Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah
    A programmable VLSI array with constant I/O pins. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:205-210 [Conf]
  22. Francky Catthoor, M. Van Swaalj, J. Rosseel, Hugo De Man
    Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:211-222 [Conf]
  23. M. Van Swaalj, Francky Catthoor, Hugo De Man
    Signal analysis and signal transformations for ASIC regular array architecture synthesis. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:223-232 [Conf]
  24. Patrice Frison, Dominique Lavenier
    Experience in the design of paralle processor arrays. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:233-242 [Conf]
  25. John V. McCanny
    On the use of most significant digit first arithmetic in the design of high performance DSP chips. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:243-260 [Conf]
  26. Jean-Michel Muller
    On-line computing: a survey and some new results. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:261-272 [Conf]
  27. Jean Duprat, Mario Fiallos Aguilar, Jean-Michel Muller, Hong-Jin Yeh
    Delays of on-line floating point operators in borrow-save representation. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:273-278 [Conf]
  28. Fawad Rauf, Hassan M. Ahmed
    Nonlinear adaptive filtering algorithms for parallel and systolic implementation. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:279-284 [Conf]
  29. D. K. Arvind
    Distributed simulation of parallel VLSI architectures. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:285-298 [Conf]
  30. Guy Durrieu, Kamel Kessaci, Michel Lemaître
    Transe: an experimental design tool. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:299-304 [Conf]
  31. Frédéric Dufaux, Murat Kunt
    Matrix Multiplication on an associative string processor: application to image compression by Gabor expansion. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:305-310 [Conf]
  32. Henri-Pierre Charles
    Loop unrolling for processors with instruction cache. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:311-316 [Conf]
  33. K. Bouazza, Joël Champeau, P. Ng, Bernard Pottier, Stéphane Rubini
    Implementing cellular automata on the ArMen machine. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:317-324 [Conf]
  34. C. Dezan, Hervé Le Verge, Patrice Quinton, Yannick Saouter
    The Alpha du Centaur environment. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:325-334 [Conf]
  35. Frédéric Rocheteau, Nicolas Halbwachs
    POLLUS: A LUSTRE based hardware design environment. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:335-346 [Conf]
  36. Paul Le Guernic
    The SIGNAL programming environment. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:347-358 [Conf]
  37. M. Schönfeld, M. Schwiegershausen, Peter Pirsch
    Synthesis of intermediate memories for the data supply to processor arrays. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:365-370 [Conf]
  38. Uwe Vehlies
    The derivation of dependence graphs from PASCAL programs for array processor design. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:371-376 [Conf]
  39. M. S. Laghari, Farzin Deravi
    Comparison of scheduling techniques for the parallel implementation of the Hough transform. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:377-382 [Conf]
  40. Alain Darte
    Two heuristics for task scheduling. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:383-0 [Conf]
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