Marc Moonen Algorithms and architectures for recursive total least squares estimation. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:39-46 [Conf]

Gur Saran Adhar, Shietung Peng Parallel algorithms for finding connected, independent and total domination in interval graphs. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:85-90 [Conf]

Tanguy Risset Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:163-174 [Conf]

Jingling Xue, Christian Lengauer Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:181-186 [Conf]

Sanjay V. Rajopadhye An improved systolic algorithm for the algebraic path problem. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:187-198 [Conf]

John V. McCanny On the use of most significant digit first arithmetic in the design of high performance DSP chips. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:243-260 [Conf]

Jean-Michel Muller On-line computing: a survey and some new results. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:261-272 [Conf]

Frédéric Dufaux, Murat Kunt Matrix Multiplication on an associative string processor: application to image compression by Gabor expansion. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:305-310 [Conf]

Henri-Pierre Charles Loop unrolling for processors with instruction cache. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:311-316 [Conf]

Uwe Vehlies The derivation of dependence graphs from PASCAL programs for array processor design. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:371-376 [Conf]

M. S. Laghari, Farzin Deravi Comparison of scheduling techniques for the parallel implementation of the Hough transform. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:377-382 [Conf]

Alain Darte Two heuristics for task scheduling. [Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:383-0 [Conf]

NOTICE1

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades

NOTICE2

The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP