Conferences in DBLP

IEEE International Workshop on Rapid System Prototyping (rsp)
2008 (conf/rsp/2008)

1. 
   Multi-dimensional Model Based Engineering Using AADL. [Citation Graph (, )][DBLP]
   
   
2. 
   Testing Automotive System Prototypes Far before Driving on the Proving Ground. [Citation Graph (, )][DBLP]
   
   
3. 
   The RTSJ for Prototyping Real-Time Systems: A Case Study. [Citation Graph (, )][DBLP]
   
   
4. 
   RealSpec: An Executable Specification Language for Prototyping Concurrent Systems. [Citation Graph (, )][DBLP]
   
   
5. 
   Using MDE for the Rapid Prototyping of Space Critical Systems. [Citation Graph (, )][DBLP]
   
   
6. 
   Functional DIF for Rapid Prototyping. [Citation Graph (, )][DBLP]
   
   
7. 
   High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping. [Citation Graph (, )][DBLP]
   
   
8. 
   Software for Multi Processor System on Chip: Moving an MPEG4 Decoder from Generic RISC Platforms to CELL. [Citation Graph (, )][DBLP]
   
   
9. 
   Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers. [Citation Graph (, )][DBLP]
   
   
10. 
    Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels. [Citation Graph (, )][DBLP]
    
    
11. 
    An Automated Design Flow for NoC-based MPSoCs on FPGA. [Citation Graph (, )][DBLP]
    
    
12. 
    Integrating Abstract NoC Models within MPSoC Design. [Citation Graph (, )][DBLP]
    
    
13. 
    Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology. [Citation Graph (, )][DBLP]
    
    
14. 
    A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support. [Citation Graph (, )][DBLP]
    
    
15. 
    Design Flow for Reconfiguration Based on the Overlaying Concept. [Citation Graph (, )][DBLP]
    
    
16. 
    A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller. [Citation Graph (, )][DBLP]
    
    
17. 
    Requirement Traceability in Software Development Process: An Empirical Approach. [Citation Graph (, )][DBLP]
    
    
18. 
    Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip. [Citation Graph (, )][DBLP]
    
    
19. 
    A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping. [Citation Graph (, )][DBLP]
    
    
20. 
    From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. [Citation Graph (, )][DBLP]
    
    
21. 
    A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates. [Citation Graph (, )][DBLP]
    
    
22. 
    Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. [Citation Graph (, )][DBLP]
    
    
23. 
    Implementation Strategies for Statistical Codec Designs in H.264/AVC Standard. [Citation Graph (, )][DBLP]
    
    
24. 
    ASIP-controlled Inverse Integer Transform for H.264/AVC Compression. [Citation Graph (, )][DBLP]
    
    
25. 
    A Novel System-on-Chip Architecture for Efficient Image Processing. [Citation Graph (, )][DBLP]
    
    
26. 
    Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine. [Citation Graph (, )][DBLP]
    
    
27. 
    Flexible Software-Hardware Network Intrusion Detection System. [Citation Graph (, )][DBLP]
    
    
28. 
    MAJIC: A Java Application for Controlling Multiple, Heterogeneous Robotic Agents. [Citation Graph (, )][DBLP]
    
    
29. 
    Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. [Citation Graph (, )][DBLP]
    
    
30. 
    Author Index. [Citation Graph (, )][DBLP]
    
    
31. 
    Publisher's Information. [Citation Graph (, )][DBLP]