Conferences in DBLP

SAMOS Workshops (samos)
2008 (conf/samos/2008)

1. 
   Can They Be Fixed: Some Thoughts After 40 Years in the Business. [Citation Graph (, )][DBLP]
   
   
2. 
   On the Benefit of Caching Traffic Flow Data in the Link Buffer. [Citation Graph (, )][DBLP]
   
   
3. 
   Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. [Citation Graph (, )][DBLP]
   
   
4. 
   Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic. [Citation Graph (, )][DBLP]
   
   
5. 
   Scalable Architecture for Prefix Preserving Anonymization of IP Addresses. [Citation Graph (, )][DBLP]
   
   
6. 
   Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology. [Citation Graph (, )][DBLP]
   
   
7. 
   Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. [Citation Graph (, )][DBLP]
   
   
8. 
   802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec. [Citation Graph (, )][DBLP]
   
   
9. 
   A Real-Time Programming Model for Heterogeneous MPSoCs. [Citation Graph (, )][DBLP]
   
   
10. 
    A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation. [Citation Graph (, )][DBLP]
    
    
11. 
    A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs. [Citation Graph (, )][DBLP]
    
    
12. 
    Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors. [Citation Graph (, )][DBLP]
    
    
13. 
    Area Reliability Trade-Off in Improved Reed Muller Coding. [Citation Graph (, )][DBLP]
    
    
14. 
    Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set. [Citation Graph (, )][DBLP]
    
    
15. 
    ASIP-eFPGA Architecture for Multioperable GNSS Receivers. [Citation Graph (, )][DBLP]
    
    
16. 
    Introduction to System Level Design for Heterogeneous Systems. [Citation Graph (, )][DBLP]
    
    
17. 
    Streaming Systems in FPGAs. [Citation Graph (, )][DBLP]
    
    
18. 
    Heterogeneous Design in Functional DIF. [Citation Graph (, )][DBLP]
    
    
19. 
    Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. [Citation Graph (, )][DBLP]
    
    
20. 
    Evaluation of ASIPs Design with LISATek. [Citation Graph (, )][DBLP]
    
    
21. 
    High Level Loop Transformations for Systematic Signal Processing Embedded Applications. [Citation Graph (, )][DBLP]
    
    
22. 
    Memory-Centric Hardware Synthesis from Dataflow Models. [Citation Graph (, )][DBLP]
    
    
23. 
    Introduction to Programming Multicores. [Citation Graph (, )][DBLP]
    
    
24. 
    Design Issues in Parallel Array Languages for Shared Memory. [Citation Graph (, )][DBLP]
    
    
25. 
    An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. [Citation Graph (, )][DBLP]
    
    
26. 
    Climate and Biological Sensor Network. [Citation Graph (, )][DBLP]
    
    
27. 
    Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors. [Citation Graph (, )][DBLP]
    
    
28. 
    Application Server for Wireless Sensor Networks. [Citation Graph (, )][DBLP]
    
    
29. 
    Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks. [Citation Graph (, )][DBLP]
    
    
30. 
    Signature-Based Calibration of Analytical System-Level Performance Models. [Citation Graph (, )][DBLP]
    
    
31. 
    System-Level Design Space Exploration of Dynamic Reconfigurable Architectures. [Citation Graph (, )][DBLP]
    
    
32. 
    Intellectual Property Protection for Embedded Sensor Nodes. [Citation Graph (, )][DBLP]