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Conferences in DBLP
What Else Is Broken? Can We Fix It? [Citation Graph (, )][DBLP]
Programmable and Scalable Architecture for Graphics Processing Units. [Citation Graph (, )][DBLP]
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. [Citation Graph (, )][DBLP]
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. [Citation Graph (, )][DBLP]
Programmable Accelerators for Reconfigurable Video Decoder. [Citation Graph (, )][DBLP]
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study. [Citation Graph (, )][DBLP]
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks. [Citation Graph (, )][DBLP]
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC. [Citation Graph (, )][DBLP]
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. [Citation Graph (, )][DBLP]
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. [Citation Graph (, )][DBLP]
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA. [Citation Graph (, )][DBLP]
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. [Citation Graph (, )][DBLP]
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata. [Citation Graph (, )][DBLP]
Prediction in Dynamic SDRAM Controller Policies. [Citation Graph (, )][DBLP]
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. [Citation Graph (, )][DBLP]
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration. [Citation Graph (, )][DBLP]
Modeling Scalable SIMD DSPs in LISA. [Citation Graph (, )][DBLP]
NoGAP: A Micro Architecture Construction Framework. [Citation Graph (, )][DBLP]
A Comparison of NoTA and GENESYS. [Citation Graph (, )][DBLP]
Introduction to Instruction-Set Customization. [Citation Graph (, )][DBLP]
Constraint-Driven Identification of Application Specific Instructions in the DURASE System. [Citation Graph (, )][DBLP]
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). [Citation Graph (, )][DBLP]
Runtime Adaptive Extensible Embedded Processors - A Survey. [Citation Graph (, )][DBLP]
Introduction to the Future of Reconfigurable Computing and Processor Architectures. [Citation Graph (, )][DBLP]
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems. [Citation Graph (, )][DBLP]
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study. [Citation Graph (, )][DBLP]
Reconfigurable Multicore Server Processors for Low Power Operation. [Citation Graph (, )][DBLP]
Reconfigurable Computing in the New Age of Parallelism. [Citation Graph (, )][DBLP]
Reconfigurable Multithreading Architectures: A Survey. [Citation Graph (, )][DBLP]
Introduction to Mastering Cell BE and GPU Execution Platforms. [Citation Graph (, )][DBLP]
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. [Citation Graph (, )][DBLP]
Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs. [Citation Graph (, )][DBLP]
Experiences with Cell-BE and GPU for Tomography. [Citation Graph (, )][DBLP]
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell. [Citation Graph (, )][DBLP]
Exploiting Locality on the Cell/B.E. through Bypassing. [Citation Graph (, )][DBLP]
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System. [Citation Graph (, )][DBLP]
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