Conferences in DBLP

SAMOS Workshops (samos)
2008 (conf/samos/2008ic)

1. 
   Challenges in embedded system simulation. [Citation Graph (, )][DBLP]
   
   
2. 
   Towards unified mechanisms for inter-processor communication. [Citation Graph (, )][DBLP]
   
   
3. 
   PicoServer - building a compact energy efficient multiprocessor. [Citation Graph (, )][DBLP]
   
   
4. 
   A general model of concurrency and its implementation as many-core dynamic RISC processors. [Citation Graph (, )][DBLP]
   
   
5. 
   A parameterized dataflow language extension for embedded streaming systems. [Citation Graph (, )][DBLP]
   
   
6. 
   An architecture for the simultaneous execution of hard real-time threads. [Citation Graph (, )][DBLP]
   
   
7. 
   An adaptive bloom filter cache partitioning scheme for multicore architectures. [Citation Graph (, )][DBLP]
   
   
8. 
   On brain-inspired hybrid topologies for nano-architectures - a Rent's rule approach -. [Citation Graph (, )][DBLP]
   
   
9. 
   Realizing reconfigurable mesh algorithms on softcore arrays. [Citation Graph (, )][DBLP]
   
   
10. 
    A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. [Citation Graph (, )][DBLP]
    
    
11. 
    Systematic design space exploration for customisable multi-processor architectures. [Citation Graph (, )][DBLP]
    
    
12. 
    Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions. [Citation Graph (, )][DBLP]
    
    
13. 
    Multi-objective routing and topology optimization in networked embedded systems. [Citation Graph (, )][DBLP]
    
    
14. 
    ImpBench: A novel benchmark suite for biomedical, microelectronic implants. [Citation Graph (, )][DBLP]
    
    
15. 
    Perceptual feature based music classification - A DSP perspective for a new type of application. [Citation Graph (, )][DBLP]
    
    
16. 
    Software defined radio implementation of K-best list sphere detector algorithm. [Citation Graph (, )][DBLP]
    
    
17. 
    Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm. [Citation Graph (, )][DBLP]
    
    
18. 
    An instruction set extension for java bytecodes translation acceleration. [Citation Graph (, )][DBLP]
    
    
19. 
    Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices. [Citation Graph (, )][DBLP]
    
    
20. 
    Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core^TM 2 Duo processor. [Citation Graph (, )][DBLP]
    
    
21. 
    Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]
    
    
22. 
    An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods. [Citation Graph (, )][DBLP]
    
    
23. 
    Efficient management of speculative data in hardware transactional memory systems. [Citation Graph (, )][DBLP]
    
    
24. 
    An intermediate format for automatic generation of MPSoC virtual prototypes. [Citation Graph (, )][DBLP]
    
    
25. 
    Exploiting partial reconfiguration for flexible software debugging. [Citation Graph (, )][DBLP]
    
    
26. 
    A cost model for partial dynamic reconfiguration. [Citation Graph (, )][DBLP]
    
    
27. 
    Reconfigurable design with clock gating. [Citation Graph (, )][DBLP]
    
    
28. 
    A centralized cache miss driven technique to improve processor power dissipation. [Citation Graph (, )][DBLP]
    
    
29. 
    A priority-expression-based burst scheduling of memory reordering access. [Citation Graph (, )][DBLP]
    
    
30. 
    Improving memory subsystem performance in network processors with smart packet segmentation. [Citation Graph (, )][DBLP]
    
    
31. 
    Improving TLB energy for java applications on JVM. [Citation Graph (, )][DBLP]