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Conferences in DBLP
"Slower than you think" - The evolution of processor and SoC architectures. [Citation Graph (, )][DBLP]
Mobile visual computing. [Citation Graph (, )][DBLP]
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. [Citation Graph (, )][DBLP]
High-speed FPGA-based implementations of a Genetic Algorithm. [Citation Graph (, )][DBLP]
OpenMP extensions for FPGA accelerators. [Citation Graph (, )][DBLP]
High-level synthesis for the design of FPGA-based signal processing systems. [Citation Graph (, )][DBLP]
Instruction scheduling for VLIW processors under variation scenario. [Citation Graph (, )][DBLP]
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. [Citation Graph (, )][DBLP]
Instruction-based reuse-distance prediction for effective cache management. [Citation Graph (, )][DBLP]
Adaptive simulation sampling using an Autoregressive framework. [Citation Graph (, )][DBLP]
An emulation-based real-time power profiling unit for embedded software. [Citation Graph (, )][DBLP]
A timed HW/SW coemulation technique for fast yet accurate system verification. [Citation Graph (, )][DBLP]
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. [Citation Graph (, )][DBLP]
Generation and calibration of compositional performance analysis models for multi-processor systems. [Citation Graph (, )][DBLP]
Performance evaluation of concurrently executing parallel applications on multi-processor systems. [Citation Graph (, )][DBLP]
Manycore performance analysis using timed configuration graphs. [Citation Graph (, )][DBLP]
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques. [Citation Graph (, )][DBLP]
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. [Citation Graph (, )][DBLP]
Synchronization on heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]
Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs. [Citation Graph (, )][DBLP]
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. [Citation Graph (, )][DBLP]
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. [Citation Graph (, )][DBLP]
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. [Citation Graph (, )][DBLP]
Customizing wide-SIMD architectures for H.264. [Citation Graph (, )][DBLP]
Parallel implementation of convolution encoder for software defined radio on DSP architecture. [Citation Graph (, )][DBLP]
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