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Conferences in DBLP

SAMOS Workshops (samos)
2009 (conf/samos/2009ic)


  1. "Slower than you think" - The evolution of processor and SoC architectures. [Citation Graph (, )][DBLP]


  2. Mobile visual computing. [Citation Graph (, )][DBLP]


  3. A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. [Citation Graph (, )][DBLP]


  4. High-speed FPGA-based implementations of a Genetic Algorithm. [Citation Graph (, )][DBLP]


  5. OpenMP extensions for FPGA accelerators. [Citation Graph (, )][DBLP]


  6. High-level synthesis for the design of FPGA-based signal processing systems. [Citation Graph (, )][DBLP]


  7. Instruction scheduling for VLIW processors under variation scenario. [Citation Graph (, )][DBLP]


  8. A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. [Citation Graph (, )][DBLP]


  9. Instruction-based reuse-distance prediction for effective cache management. [Citation Graph (, )][DBLP]


  10. Adaptive simulation sampling using an Autoregressive framework. [Citation Graph (, )][DBLP]


  11. An emulation-based real-time power profiling unit for embedded software. [Citation Graph (, )][DBLP]


  12. A timed HW/SW coemulation technique for fast yet accurate system verification. [Citation Graph (, )][DBLP]


  13. RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. [Citation Graph (, )][DBLP]


  14. Generation and calibration of compositional performance analysis models for multi-processor systems. [Citation Graph (, )][DBLP]


  15. Performance evaluation of concurrently executing parallel applications on multi-processor systems. [Citation Graph (, )][DBLP]


  16. Manycore performance analysis using timed configuration graphs. [Citation Graph (, )][DBLP]


  17. Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques. [Citation Graph (, )][DBLP]


  18. Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. [Citation Graph (, )][DBLP]


  19. Synchronization on heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  20. Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs. [Citation Graph (, )][DBLP]


  21. FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. [Citation Graph (, )][DBLP]


  22. High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. [Citation Graph (, )][DBLP]


  23. Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. [Citation Graph (, )][DBLP]


  24. Customizing wide-SIMD architectures for H.264. [Citation Graph (, )][DBLP]


  25. Parallel implementation of convolution encoder for software defined radio on DSP architecture. [Citation Graph (, )][DBLP]

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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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