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Conferences in DBLP

Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) (sbac-pad)
2006 (conf/sbac-pad/2006)


  1. ParTriCluster: A Scalable Parallel Algorithm for Gene Expression Analysis. [Citation Graph (, )][DBLP]


  2. Towards Production Code Effective Portability among Vector Machines and Microprocessor-Based Architectures. [Citation Graph (, )][DBLP]


  3. Data Segmentation Management Infrastructure in a Database Grid. [Citation Graph (, )][DBLP]


  4. Detecting Malicious Manipulation in Grid Environments. [Citation Graph (, )][DBLP]


  5. Policy-based Resource Allocation in Hierarchical Virtual Organizations for Global Grids. [Citation Graph (, )][DBLP]


  6. A Speculative Trace Reuse Architecture with Reduced Hardware Requirements. [Citation Graph (, )][DBLP]


  7. Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. [Citation Graph (, )][DBLP]


  8. The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture. [Citation Graph (, )][DBLP]


  9. GerpavGrid: using the Grid to maintain the city road system. [Citation Graph (, )][DBLP]


  10. A Run-time System for Efficient Execution of Scientific Workflows on Distributed Environments. [Citation Graph (, )][DBLP]


  11. Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush. [Citation Graph (, )][DBLP]


  12. Characterizing the Performance of Data Management Systems on Hyper-Threaded Architectures. [Citation Graph (, )][DBLP]


  13. Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach. [Citation Graph (, )][DBLP]


  14. Scalable Value-Cache Based Compression Schemes for Multiprocessors. [Citation Graph (, )][DBLP]


  15. Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. [Citation Graph (, )][DBLP]


  16. Applying the zeros switch-off technique to reduce static energy in data caches. [Citation Graph (, )][DBLP]


  17. 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. [Citation Graph (, )][DBLP]


  18. Combining Source Routing and Dynamic Fault Tolerance. [Citation Graph (, )][DBLP]


  19. Runtime System Support for Running Applications with Dynamic and Asynchronous Task Parallelism in Software DSM Systems. [Citation Graph (, )][DBLP]


  20. Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference. [Citation Graph (, )][DBLP]


  21. Reconfigurable System with Virtuoso Real-Time Kernel and TEV Environment. [Citation Graph (, )][DBLP]


  22. Virtual-Machine-based Intrusion Detection on File-aware Block Level Storage. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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