Conferences in DBLP

Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) (sbac-pad)
2008 (conf/sbac-pad/2008)

1. 
   Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures. [Citation Graph (, )][DBLP]
   
   
2. 
   Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt? [Citation Graph (, )][DBLP]
   
   
3. 
   An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm. [Citation Graph (, )][DBLP]
   
   
4. 
   On Simulated Annealing for the Scheduling of Parallel Applications. [Citation Graph (, )][DBLP]
   
   
5. 
   Controlling Processes Reassignment in BSP Applications. [Citation Graph (, )][DBLP]
   
   
6. 
   A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation. [Citation Graph (, )][DBLP]
   
   
7. 
   A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore Systems. [Citation Graph (, )][DBLP]
   
   
8. 
   Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. [Citation Graph (, )][DBLP]
   
   
9. 
   ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch. [Citation Graph (, )][DBLP]
   
   
10. 
    Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture. [Citation Graph (, )][DBLP]
    
    
11. 
    Parallel Verified Linear System Solver for Uncertain Input Data. [Citation Graph (, )][DBLP]
    
    
12. 
    Applying Virtualization and System Management in a Cluster to Implement an Automated Emulation Testbed for Grid Applications. [Citation Graph (, )][DBLP]
    
    
13. 
    Hiding Communication Delays in Clustered Microarchitectures. [Citation Graph (, )][DBLP]
    
    
14. 
    Software Synthesis for Hard Real-Time Embedded Systems with Energy Constraints. [Citation Graph (, )][DBLP]
    
    
15. 
    A Segmented Bloom Filter Algorithm for Efficient Predictors. [Citation Graph (, )][DBLP]
    
    
16. 
    Measuring Operating System Overhead on CMT Processors. [Citation Graph (, )][DBLP]
    
    
17. 
    Aspect-Based Patterns for Grid Programming. [Citation Graph (, )][DBLP]
    
    
18. 
    A Reconfigurable Run-Time System for Filter-Stream Applications. [Citation Graph (, )][DBLP]
    
    
19. 
    Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design. [Citation Graph (, )][DBLP]
    
    
20. 
    Performance Sensitivity of NUCA Caches to On-Chip Network Parameters. [Citation Graph (, )][DBLP]
    
    
21. 
    A Software Transactional Memory System for an Asymmetric Processor Architecture. [Citation Graph (, )][DBLP]
    
    
22. 
    Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations. [Citation Graph (, )][DBLP]