Conferences in DBLP

(sbcci)
2008 (conf/sbcci/2008)

1. 
   Sizing CMOS circuits by means of the gm/ID methodology and a compact model. [Citation Graph (, )][DBLP]
   
   
2. 
   Synergistic modeling and optimization for nanometer IC design/manufacturing integration. [Citation Graph (, )][DBLP]
   
   
3. 
   Test Methods For Sigma-Delta Data Converters and Related Devices. [Citation Graph (, )][DBLP]
   
   
4. 
   Highly integrated, re-configurable RF front-ends in deep sub-micron CMOS: (with an example of a WCDMA, GSM/GPRS/EDGE receiver without inter-stage SAW filter). [Citation Graph (, )][DBLP]
   
   
5. 
   System-level design technologies for heterogeneous distributed systems. [Citation Graph (, )][DBLP]
   
   
6. 
   Lithography friendly routing: from construct-by-correction to correct-by-construction. [Citation Graph (, )][DBLP]
   
   
7. 
   Time-domain analog signal processing techniques. [Citation Graph (, )][DBLP]
   
   
8. 
   System design for 3D Silicon integration. [Citation Graph (, )][DBLP]
   
   
9. 
   Challenges of the nanoscale era. [Citation Graph (, )][DBLP]
   
   
10. 
    Full-chip routing system for reducing Cu CMP & ECP variation. [Citation Graph (, )][DBLP]
    
    
11. 
    Metal filling impact on standard cells: definition of the metal fill corner concept. [Citation Graph (, )][DBLP]
    
    
12. 
    A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures. [Citation Graph (, )][DBLP]
    
    
13. 
    A new march sequence to fit DDR SDRAM test in burst mode. [Citation Graph (, )][DBLP]
    
    
14. 
    An efficient test and characterization approach for nanowire-based architectures. [Citation Graph (, )][DBLP]
    
    
15. 
    Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. [Citation Graph (, )][DBLP]
    
    
16. 
    The performance of pollution control victim cache for embedded systems. [Citation Graph (, )][DBLP]
    
    
17. 
    Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems. [Citation Graph (, )][DBLP]
    
    
18. 
    An approximate algorithm for the multiple constant multiplications problem. [Citation Graph (, )][DBLP]
    
    
19. 
    Area optimization algorithms in high-speed digital FIR filter synthesis. [Citation Graph (, )][DBLP]
    
    
20. 
    A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. [Citation Graph (, )][DBLP]
    
    
21. 
    A 40mhz 70db gain variable gain amplifier design using the gm/id design method. [Citation Graph (, )][DBLP]
    
    
22. 
    A 2.7ua sub1-v voltage reference. [Citation Graph (, )][DBLP]
    
    
23. 
    A wide band CMOS differential voltage-controlled ring oscillator. [Citation Graph (, )][DBLP]
    
    
24. 
    RBF circuits based on folded cascode differential pairs. [Citation Graph (, )][DBLP]
    
    
25. 
    A current limiter for DC/DC regulators with internal compensation for process and temperature. [Citation Graph (, )][DBLP]
    
    
26. 
    Current mode read-out circuit for infrared photodiode applications in 0.35 mum cmos. [Citation Graph (, )][DBLP]
    
    
27. 
    Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors. [Citation Graph (, )][DBLP]
    
    
28. 
    Encountering gate oxide breakdown with shadow transistors to increase reliability. [Citation Graph (, )][DBLP]
    
    
29. 
    A novel scheme to reduce short-circuit power in mesh-based clock architectures. [Citation Graph (, )][DBLP]
    
    
30. 
    Power and performance tradeoffs with process variation resilient adaptive cache architectures. [Citation Graph (, )][DBLP]
    
    
31. 
    Power management techniques for very low consumption and EMI reduction in automotive applications. [Citation Graph (, )][DBLP]
    
    
32. 
    A coloured petri net based approach for estimating execution time and energy consumption in embedded systems. [Citation Graph (, )][DBLP]
    
    
33. 
    A novel AES cryptographic core highly resistant to differential power analysis attacks. [Citation Graph (, )][DBLP]
    
    
34. 
    An improved and automated design tool for the optimization of CMOS OTAs using geometric programming. [Citation Graph (, )][DBLP]
    
    
35. 
    CMOS op-amp power optimization in all regions of inversion using geometric programming. [Citation Graph (, )][DBLP]
    
    
36. 
    Systematic methodology for the design of Seevinck's CMOS log-domain integrators. [Citation Graph (, )][DBLP]
    
    
37. 
    BenCGen: a digital circuit generation tool for benchmarks. [Citation Graph (, )][DBLP]
    
    
38. 
    A simplified executable model to evaluate latency and throughput of networks-on-chip. [Citation Graph (, )][DBLP]
    
    
39. 
    Executable formal specification and validation of NoC communication infrastructures. [Citation Graph (, )][DBLP]
    
    
40. 
    MOTIM: an industrial application using nocs. [Citation Graph (, )][DBLP]
    
    
41. 
    Fault-tolerance in FPGA's through CRC voting. [Citation Graph (, )][DBLP]
    
    
42. 
    Evaluating the robustness of secure triple track logic through prototyping. [Citation Graph (, )][DBLP]
    
    
43. 
    Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications. [Citation Graph (, )][DBLP]
    
    
44. 
    Self-adaptable slew rate control output buffer for embedded microcontroller port applications. [Citation Graph (, )][DBLP]
    
    
45. 
    Efficient dynamic reconfiguration for multi-context embedded FPGA. [Citation Graph (, )][DBLP]
    
    
46. 
    Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV. [Citation Graph (, )][DBLP]
    
    
47. 
    A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter. [Citation Graph (, )][DBLP]
    
    
48. 
    High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV. [Citation Graph (, )][DBLP]
    
    
49. 
    Analog hardware implementation of a vector quantizer for focal-plane image compression. [Citation Graph (, )][DBLP]
    
    
50. 
    A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis. [Citation Graph (, )][DBLP]