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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2008 (conf/slip/2008)


  1. Interconnection lengths and delays estimation for communication links in FPGAs. [Citation Graph (, )][DBLP]


  2. Efficient tiling patterns for reconfigurable gate arrays. [Citation Graph (, )][DBLP]


  3. Timing optimization in logic with interconnect. [Citation Graph (, )][DBLP]


  4. Revisiting fidelity: a case of elmore-based Y-routing trees. [Citation Graph (, )][DBLP]


  5. Multi-core architectures and streaming applications. [Citation Graph (, )][DBLP]


  6. Parallel vs. serial on-chip communication. [Citation Graph (, )][DBLP]


  7. Global interconnections in FPGAs: modeling and performance analysis. [Citation Graph (, )][DBLP]


  8. Circuit and physical design of the MDGRAPE-4 on-chip network links. [Citation Graph (, )][DBLP]


  9. The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk. [Citation Graph (, )][DBLP]


  10. Sidewinder: a scalable ILP-based router. [Citation Graph (, )][DBLP]


  11. The next resource war: computation vs. communication. [Citation Graph (, )][DBLP]


  12. Rent's rule and parallel programs: characterizing network traffic behavior. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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