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Conferences in DBLP

Advanced Courses (ac)
2002 (conf/ac/2002chd)

  1. Igor Benko, Jo C. Ebergen
    Composing Snippets. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:1-33 [Conf]
  2. Mark B. Josephs, Dennis P. Furey
    A Programming Approach to the Design of Asynchronous Logic Blocks. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:34-60 [Conf]
  3. Victor Varshavsky, Vyacheslav Marakhovsky
    GALA (Globally Asynchronous - Locally Arbitrary) Design. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:61-107 [Conf]
  4. Josep Carmona, Jordi Cortadella, Enric Pastor
    Synthesis of Reactive Systems: Application to Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:108-151 [Conf]
  5. Walter Vogler, Ralf Wollowski
    Decomposition in Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:152-190 [Conf]
  6. William W. LaRue, Sherry Solden, Bishnupriya Bhattacharya
    Functional and Performance Modeling of Concurrency in VCC. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:191-227 [Conf]
  7. Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
    Modeling and Designing Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:228-273 [Conf]
  8. Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen
    Timed Verification of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:274-312 [Conf]
  9. Peter A. Beerel, Aiguo Xie
    Performance Analysis of Asynchronous Circuits Using Markov Chains. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:313-344 [Conf]
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