Conferences in DBLP

Conference on Very Large Scale Integration (VLSI) (vlsi)
2007 (conf/vlsi/2007soc)

1. 
   Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. [Citation Graph (, )][DBLP]
   
   
2. 
   Neuromorphic building blocks for adaptable cortical feature maps. [Citation Graph (, )][DBLP]
   
   
3. 
   An analog programmable multi-dimensional radial basis function based classifier. [Citation Graph (, )][DBLP]
   
   
4. 
   ReCPU: A parallel and pipelined architecture for regular expression matching. [Citation Graph (, )][DBLP]
   
   
5. 
   Use of gray decoding for implementation of symmetric functions. [Citation Graph (, )][DBLP]
   
   
6. 
   Parametric structure-preserving model order reduction. [Citation Graph (, )][DBLP]
   
   
7. 
   Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators. [Citation Graph (, )][DBLP]
   
   
8. 
   First order quasi-static SOI MOSFET channel capacitance model. [Citation Graph (, )][DBLP]
   
   
9. 
   Regression based circuit matrix models for accurate performance estimation of analog circuits. [Citation Graph (, )][DBLP]
   
   
10. 
    A software-supported methodology for designing high-performance 3D FPGA architectures. [Citation Graph (, )][DBLP]
    
    
11. 
    Estimating design time for system circuits. [Citation Graph (, )][DBLP]
    
    
12. 
    Transparent acceleration of data dependent instructions for general purpose processors. [Citation Graph (, )][DBLP]
    
    
13. 
    VLSI models of network-on-chip interconnect. [Citation Graph (, )][DBLP]
    
    
14. 
    Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. [Citation Graph (, )][DBLP]
    
    
15. 
    AC-coupling strategy for high-speed transceivers of 10Gbps and beyond. [Citation Graph (, )][DBLP]
    
    
16. 
    SWORD: A SAT like prover using word level information. [Citation Graph (, )][DBLP]
    
    
17. 
    Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. [Citation Graph (, )][DBLP]
    
    
18. 
    Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. [Citation Graph (, )][DBLP]
    
    
19. 
    A high-driving class-AB buffer amplifier with a new pseudo source follower. [Citation Graph (, )][DBLP]
    
    
20. 
    A new analytical approach of the impact of jitter on continuous time delta sigma converters. [Citation Graph (, )][DBLP]
    
    
21. 
    Transistor level automatic layout generator for non-complementary CMOS cells. [Citation Graph (, )][DBLP]
    
    
22. 
    Computing and design for software and silicon manufacturing. [Citation Graph (, )][DBLP]
    
    
23. 
    An adaptive genetic algorithm for dynamically reconfigurable modules allocation. [Citation Graph (, )][DBLP]
    
    
24. 
    New tool support and architectures in adaptive reconfigurable computing. [Citation Graph (, )][DBLP]
    
    
25. 
    Rate-based scheduling policy for QoS flows in networks on chip. [Citation Graph (, )][DBLP]
    
    
26. 
    Parallelized radix-2 scalable Montgomery multiplier. [Citation Graph (, )][DBLP]
    
    
27. 
    An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. [Citation Graph (, )][DBLP]
    
    
28. 
    Simulation of hybrid computer architectures: simulators, methodologies and recommendations. [Citation Graph (, )][DBLP]
    
    
29. 
    New parallel programming techniques for hardware design. [Citation Graph (, )][DBLP]
    
    
30. 
    Efficient DSP algorithm development for FPGA and ASIC technologies. [Citation Graph (, )][DBLP]
    
    
31. 
    Incremental placement for structured ASICs using the transportation problem. [Citation Graph (, )][DBLP]
    
    
32. 
    Test data compression and TAM design. [Citation Graph (, )][DBLP]
    
    
33. 
    Dynamic gates with hysteresis and configurable noise tolerance. [Citation Graph (, )][DBLP]
    
    
34. 
    A low-power deblocking filter architecture for H.264 advanced video coding. [Citation Graph (, )][DBLP]
    
    
35. 
    The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. [Citation Graph (, )][DBLP]
    
    
36. 
    An efficient H.264 intra frame coder system design. [Citation Graph (, )][DBLP]
    
    
37. 
    Qualification of behavioral level design validation for AMS & RF SoCs. [Citation Graph (, )][DBLP]
    
    
38. 
    Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack. [Citation Graph (, )][DBLP]
    
    
39. 
    Impact of hardware emulation on the verification quality improvement. [Citation Graph (, )][DBLP]
    
    
40. 
    Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model. [Citation Graph (, )][DBLP]
    
    
41. 
    Power optimization for conditional task graphs in DVS enabled multiprocessor systems. [Citation Graph (, )][DBLP]
    
    
42. 
    A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes. [Citation Graph (, )][DBLP]
    
    
43. 
    Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 mum CMO S. [Citation Graph (, )][DBLP]
    
    
44. 
    A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD. [Citation Graph (, )][DBLP]
    
    
45. 
    A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. [Citation Graph (, )][DBLP]
    
    
46. 
    Low power on-chip thermal sensors based on wires. [Citation Graph (, )][DBLP]
    
    
47. 
    A low-power CAM using a 12-transistor design cell. [Citation Graph (, )][DBLP]
    
    
48. 
    Improvement of dual rail logic as a countermeasure against DPA. [Citation Graph (, )][DBLP]
    
    
49. 
    A VHDL based approach for fast and accurate energy consumption estimations. [Citation Graph (, )][DBLP]
    
    
50. 
    Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis. [Citation Graph (, )][DBLP]
    
    
51. 
    High speed SOC design for blowfish cryptographic algorithm. [Citation Graph (, )][DBLP]
    
    
52. 
    Implementing cellular automata modeled applications on network-on-chip platforms. [Citation Graph (, )][DBLP]
    
    
53. 
    Optimum IR drop models for estimation of metal resource requirements for power distribution network. [Citation Graph (, )][DBLP]
    
    
54. 
    Impact of task migration in NoC-based MPSoCs for soft real-time applications. [Citation Graph (, )][DBLP]
    
    
55. 
    A Flexible Design Flow for a Low Power RFID Tag. [Citation Graph (, )][DBLP]
    
    
56. 
    Co-synthesis of custom on-chip bus and memory for MPSoC architectures. [Citation Graph (, )][DBLP]
    
    
57. 
    An HDTV H.264 deblocking filter in FPGA with RGB video output. [Citation Graph (, )][DBLP]
    
    
58. 
    Efficient timing closure with a transistor level design flow. [Citation Graph (, )][DBLP]
    
    
59. 
    Hybrid multiplierless FIR filter architecture based on NEDA. [Citation Graph (, )][DBLP]
    
    
60. 
    A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. [Citation Graph (, )][DBLP]