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Conferences in DBLP

VLSI Design (vlsid)
2009 (conf/vlsid/2009)


  1. A Decade of Platform-Based Design: A look backwards, a look forwards. [Citation Graph (, )][DBLP]


  2. Analog IC Design in Nanometer CMOS Technologies. [Citation Graph (, )][DBLP]


  3. Common Power Format: A User-driven Ecosystem For Proven Low Power Design Flows. [Citation Graph (, )][DBLP]


  4. The Future of Low Power Design is Here: IEEE P1801, aka, UPF 2.0. [Citation Graph (, )][DBLP]


  5. Making Sense Out of the Potential Babble of Low Power Standards. [Citation Graph (, )][DBLP]


  6. DFX and Productivity. [Citation Graph (, )][DBLP]


  7. Computational Lithography - Moore Bang for your Buck. [Citation Graph (, )][DBLP]


  8. Made for India Forum. [Citation Graph (, )][DBLP]


  9. Why is Design Automation and Reuse of Analog Designs Increasingly Trailing the Digital World? [Citation Graph (, )][DBLP]


  10. EDA Made-in-India: Fact or Fiction? [Citation Graph (, )][DBLP]


  11. Solutions for a small car - Made for India and Made in India. [Citation Graph (, )][DBLP]


  12. Accelerating Embedded System Design. [Citation Graph (, )][DBLP]


  13. Defect Aware to Power Conscious Tests - The New DFT Landscape. [Citation Graph (, )][DBLP]


  14. Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits. [Citation Graph (, )][DBLP]


  15. Power Reduction Techniques and Flows at RTL and System Level. [Citation Graph (, )][DBLP]


  16. Security and Dependability of Embedded Systems: A Computer Architects' Perspective. [Citation Graph (, )][DBLP]


  17. Design for Manufacturability and Reliability in Nano Era. [Citation Graph (, )][DBLP]


  18. Negative Feedback System and Circuit Design. [Citation Graph (, )][DBLP]


  19. Synthesis & Testing for Low Power. [Citation Graph (, )][DBLP]


  20. Power Management for Mobile Multimedia: From Audio to Video & Games. [Citation Graph (, )][DBLP]


  21. Robust Circuit Design: Challenges and Solutions. [Citation Graph (, )][DBLP]


  22. Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. [Citation Graph (, )][DBLP]


  23. Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels. [Citation Graph (, )][DBLP]


  24. Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback. [Citation Graph (, )][DBLP]


  25. Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. [Citation Graph (, )][DBLP]


  26. Inline Assertions - Embedding Formal Properties in a Test Bench. [Citation Graph (, )][DBLP]


  27. Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. [Citation Graph (, )][DBLP]


  28. A Novel Approach for Improving the Quality of Open Fault Diagnosis. [Citation Graph (, )][DBLP]


  29. Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. [Citation Graph (, )][DBLP]


  30. Efficient Grouping of Fail Chips for Volume Yield Diagnostics. [Citation Graph (, )][DBLP]


  31. 100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS. [Citation Graph (, )][DBLP]


  32. A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS. [Citation Graph (, )][DBLP]


  33. Design of a Low Power, Variable-Resolution Flash ADC. [Citation Graph (, )][DBLP]


  34. Floorplanning for Partial Reconfiguration in FPGAs. [Citation Graph (, )][DBLP]


  35. Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. [Citation Graph (, )][DBLP]


  36. Efficient Analog/RF Layout Closure with Compaction Based Legalization. [Citation Graph (, )][DBLP]


  37. Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. [Citation Graph (, )][DBLP]


  38. Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. [Citation Graph (, )][DBLP]


  39. Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips. [Citation Graph (, )][DBLP]


  40. Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. [Citation Graph (, )][DBLP]


  41. A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference. [Citation Graph (, )][DBLP]


  42. Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies. [Citation Graph (, )][DBLP]


  43. Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple. [Citation Graph (, )][DBLP]


  44. Reversible Logic Synthesis with Output Permutation. [Citation Graph (, )][DBLP]


  45. Cone Resynthesis ECO Methodology for Multi-Million Gate Designs. [Citation Graph (, )][DBLP]


  46. A General Approach to High-Level Energy and Performance Estimation in SoCs. [Citation Graph (, )][DBLP]


  47. Exploiting Hybrid Analysis in Solving Electrical Networks. [Citation Graph (, )][DBLP]


  48. The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. [Citation Graph (, )][DBLP]


  49. New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. [Citation Graph (, )][DBLP]


  50. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. [Citation Graph (, )][DBLP]


  51. An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. [Citation Graph (, )][DBLP]


  52. Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors. [Citation Graph (, )][DBLP]


  53. Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design. [Citation Graph (, )][DBLP]


  54. Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack. [Citation Graph (, )][DBLP]


  55. Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC. [Citation Graph (, )][DBLP]


  56. Efficient Implementation of Floating-Point Reciprocator on FPGA. [Citation Graph (, )][DBLP]


  57. ReConfigurable Technologies. [Citation Graph (, )][DBLP]


  58. High-Speed On-Chip Event Counters for Embedded Systems. [Citation Graph (, )][DBLP]


  59. A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. [Citation Graph (, )][DBLP]


  60. Improved-Quality Real-Time Stereo Vision Processor. [Citation Graph (, )][DBLP]


  61. A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. [Citation Graph (, )][DBLP]


  62. A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. [Citation Graph (, )][DBLP]


  63. Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. [Citation Graph (, )][DBLP]


  64. Encoding of Floorplans through Deterministic Perturbation. [Citation Graph (, )][DBLP]


  65. Design Optimization and Automation for Secure Cryptographic Circuits. [Citation Graph (, )][DBLP]


  66. A Novel Sustained Vector Technique for the Detection of Hardware Trojans. [Citation Graph (, )][DBLP]


  67. Efficient Placement of Compressed Code for Parallel Decompression. [Citation Graph (, )][DBLP]


  68. FPGA Based High Performance Double-Precision Matrix Multiplication. [Citation Graph (, )][DBLP]


  69. FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System. [Citation Graph (, )][DBLP]


  70. A "Stitch" in Time: Accurate Timekeeping with On-Chip Compensation. [Citation Graph (, )][DBLP]


  71. Systematic Methodology for High-Level Performance Modeling of Analog Systems. [Citation Graph (, )][DBLP]


  72. A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. [Citation Graph (, )][DBLP]


  73. A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. [Citation Graph (, )][DBLP]


  74. Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]


  75. A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. [Citation Graph (, )][DBLP]


  76. A New Hardware Routing Accelerator for Multi-Terminal Nets. [Citation Graph (, )][DBLP]


  77. Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel. [Citation Graph (, )][DBLP]


  78. Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems. [Citation Graph (, )][DBLP]


  79. Code Transformations for TLB Power Reduction. [Citation Graph (, )][DBLP]


  80. Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis. [Citation Graph (, )][DBLP]


  81. Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization. [Citation Graph (, )][DBLP]


  82. Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. [Citation Graph (, )][DBLP]


  83. A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock. [Citation Graph (, )][DBLP]


  84. Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. [Citation Graph (, )][DBLP]


  85. RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. [Citation Graph (, )][DBLP]


  86. Soft Error Rates with Inertial and Logical Masking. [Citation Graph (, )][DBLP]


  87. Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study. [Citation Graph (, )][DBLP]


  88. Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. [Citation Graph (, )][DBLP]


  89. WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. [Citation Graph (, )][DBLP]


  90. An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. [Citation Graph (, )][DBLP]


  91. Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling. [Citation Graph (, )][DBLP]


  92. Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. [Citation Graph (, )][DBLP]


  93. Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. [Citation Graph (, )][DBLP]


  94. Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. [Citation Graph (, )][DBLP]


  95. An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. [Citation Graph (, )][DBLP]


  96. Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. [Citation Graph (, )][DBLP]


  97. Unified Challenges in Nano-CMOS High-Level Synthesis. [Citation Graph (, )][DBLP]


  98. Exploring the Limits of Port Reduction in Centralized Register Files. [Citation Graph (, )][DBLP]


  99. Temperature Aware Scheduling for Embedded Processors. [Citation Graph (, )][DBLP]


  100. SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  101. H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors. [Citation Graph (, )][DBLP]


  102. Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at India. [Citation Graph (, )][DBLP]


  103. Specification Driven Design of Phase Locked Loops. [Citation Graph (, )][DBLP]


  104. Coping with Variations through System-Level Design. [Citation Graph (, )][DBLP]

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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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